公开(公告)号：US11462475B2

公开(公告)日：2022-10-04

申请号：US16910748

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Seung Young Lee

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/538 ,  H01L27/118 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

公开(公告)号：US20220059571A1

公开(公告)日：2022-02-24

申请号：US17200179

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jungho Do ,  Jaewoo Seo ,  Jisu Yu

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20210184038A1

公开(公告)日：2021-06-17

申请号：US16893549

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungman Lim ,  Jaeho Park ,  Sanghoon Baek ,  Jisu YU ,  Hyeongyu You ,  Seungyoung Lee

IPC: H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes first and second active patterns, a first gate structure, first and second channels, and first and second source/drain layers. The first and second active patterns extend in a first direction, and are spaced apart in a second direction. The first gate structure extends in the second direction on the first and second active patterns. The first channels are spaced apart in a third direction on the first active pattern. The second channels are spaced apart in the third direction on the second active pattern. The first source/drain layer having a first conductivity type is formed at a side of the first gate structure to contact the first channels. The second source/drain layer having a second conductivity type is formed at a side of the first gate structure to contact the second channels. Widths in the second direction of the first and second channels are different.

公开(公告)号：US10217647B2

公开(公告)日：2019-02-26

申请号：US16032127

申请日：2018-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC: H01L21/8238 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.

公开(公告)号：US09646960B2

公开(公告)日：2017-05-09

申请号：US15046200

申请日：2016-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jung-Ho Do ,  Taejoong Song ,  Giyoung Yang ,  Seungyoung Lee ,  Jinyoung Lim

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104

Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.

公开(公告)号：US12147751B2

公开(公告)日：2024-11-19

申请号：US17360355

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman Lim ,  Hakchul Jung ,  Sanghoon Baek ,  Jaewoo Seo ,  Jisu Yu ,  Hyeongyu You

IPC: G06F30/3953 ,  G06F30/327 ,  G06F119/06 ,  H01L23/528

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

公开(公告)号：US20240303410A1

公开(公告)日：2024-09-12

申请号：US18670009

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  G06F117/12 ,  H01L23/528 ,  H01L29/423

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US12068315B2

公开(公告)日：2024-08-20

申请号：US17323707

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho Do ,  Sanghoon Baek

IPC: H01L27/06 ,  H01L23/50 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L23/5226 ,  H01L27/0688 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

公开(公告)号：US11810920B2

公开(公告)日：2023-11-07

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su Yu ,  Jae-Ho Park ,  Sanghoon Baek ,  Hyeon Gyu You ,  Seung Young Lee ,  Seung Man Lim

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

公开(公告)号：US11695002B2

公开(公告)日：2023-07-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Baek ,  Myung Gil Kang ,  Jae-Ho Park ,  Seung Young Lee

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.