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    Semiconductor memory devices including sense amplifier adjusted based on error information
    21.
    发明授权
    Semiconductor memory devices including sense amplifier adjusted based on error information 有权

    公开(公告)号：US11501823B2

    公开(公告)日：2022-11-15

    申请号：US16812850

    申请日：2020-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun Kim ,  Younghun Seo ,  Hyejung Kwon ,  Myungkyu Lee ,  Sunghye Cho

    IPC: G11C11/4091 ,  G11C11/56 ,  G11C11/4074 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    22.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220270661A1

    公开(公告)日：2022-08-25

    申请号：US17408454

    申请日：2021-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

    Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when t the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

    Semiconductor memory devices and memory systems
    23.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11068340B2

    公开(公告)日：2021-07-20

    申请号：US16792515

    申请日：2020-02-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguhn Cha ,  Hoyoung Song ,  Myungkyu Lee ,  Sunghye Cho

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME
    24.
    发明申请
    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20210194508A1

    公开(公告)日：2021-06-24

    申请号：US16987554

    申请日：2020-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

    IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

    Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS WITH ENHANCED ERROR DETECTION AND CORRECTION
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS WITH ENHANCED ERROR DETECTION AND CORRECTION 有权

    公开(公告)号：US20210191810A1

    公开(公告)日：2021-06-24

    申请号：US16934677

    申请日：2020-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

    IPC: G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    26.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240233798A9

    公开(公告)日：2024-07-11

    申请号：US18327335

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    28.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240135980A1

    公开(公告)日：2024-04-25

    申请号：US18327335

    申请日：2023-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

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