公开(公告)号：US11869818B2

公开(公告)日：2024-01-09

申请号：US17733411

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Yonghoe Cho ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Sanguk Han

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

CPC classification number: H01L22/32 ,  G01R27/2605 ,  G01R31/2818 ,  H01L22/14 ,  H01L23/3128 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20240006272A1

公开(公告)日：2024-01-04

申请号：US18296056

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyeon Kim ,  Ilhwan Kim ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/3128 ,  H01L21/565 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L23/5329 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2224/16235 ,  H01L2224/0557 ,  H01L2224/73203 ,  H01L2224/32225

Abstract: A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.

公开(公告)号：US11848293B2

公开(公告)日：2023-12-19

申请号：US17376616

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyoung Seo ,  Teak Hoon Lee ,  Chajea Jo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05008 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/16013 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18161

Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

公开(公告)号：US20230118535A1

公开(公告)日：2023-04-20

申请号：US17836142

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/544 ,  H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

公开(公告)号：US11621250B2

公开(公告)日：2023-04-04

申请号：US17571796

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US11482509B2

公开(公告)日：2022-10-25

申请号：US16906051

申请日：2020-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho You ,  Kyung Suk Oh ,  Sunkyoung Seo

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Disclosed is a semiconductor package comprising a first memory chip including a first semiconductor substrate and a first through structure that penetrates the first semiconductor substrate, a second memory chip that directly contacts a top surface of the first memory chip and includes a second semiconductor substrate and a second through structure that penetrates the second semiconductor substrate, a first dummy chip that directly contacts a top surface of the second memory chip and includes a first conductive via, a second dummy chip that directly contacts a top surface of the first dummy chip and includes a second conductive via, and a logic chip in direct contact with a top surface of the second dummy chip. The logic chip is electrically connected to the first through structure through the second conductive via, the first conductive via, and the second through structure.

公开(公告)号：US20210013181A1

公开(公告)日：2021-01-14

申请号：US16742341

申请日：2020-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.