公开(公告)号：US20230361760A1

公开(公告)日：2023-11-09

申请号：US18352171

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ahreum Kim ,  Youngo Lee ,  Minsu Kim ,  Eunhee Choi

IPC: H03K3/037 ,  G06F30/392 ,  H03K17/687 ,  H03K19/20 ,  H03K3/0233

CPC classification number: H03K3/0372 ,  G06F30/392 ,  H03K17/6872 ,  H03K19/20 ,  H03K3/02332

Abstract: A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11580288B2

公开(公告)日：2023-02-14

申请号：US16848222

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbong Kim ,  Minsu Kim ,  Yonggeol Kim

IPC: G06F30/00 ,  G06F30/398 ,  G06F30/392 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/327 ,  H01L23/522 ,  G06F30/394 ,  G06F117/04

Abstract: An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

公开(公告)号：US11545964B2

公开(公告)日：2023-01-03

申请号：US17025511

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/037 ,  G01R31/3185 ,  G01R31/3177 ,  G06F1/10 ,  H03K3/356

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US11274389B2

公开(公告)日：2022-03-15

申请号：US16054792

申请日：2018-08-03

Applicant: Samsung Electronics Co., Ltd

Inventor： Masahiro Uetsuhara ,  Takehiero Nakanishi ,  Minsu Kim ,  Shigeki Hayashi ,  Shin Kagami ,  Tomoyuki Okuno ,  Toshihiro Kamii

IPC: D06F39/00 ,  D06F39/08 ,  D06F23/04 ,  D06F33/43 ,  D06F37/12 ,  D06F37/24 ,  D06F37/26 ,  D06F103/16 ,  D06F103/18 ,  D06F103/24 ,  D06F103/26 ,  D06F103/32 ,  D06F105/48 ,  D06F105/58 ,  D06F105/60 ,  D06F101/12 ,  D06F33/48

Abstract: Disclosed herein is a top load washing machine having excellent functions while saving water. The washing machine may include a housing having a drain path installed at the bottom, a water collecting tub supported on the housing in the inside of the housing, and a rotating tub rotating on a shaft extending vertically in the inside of the water collecting tub. The rotating tub may include an outlet opening to the lower portion of a body member that can store water independently from the water collecting tub. The water collecting tub may include a first drain hole opening to the inside space of the water collecting tub, and a second drain hole communicating with the outlet. The drain path may include a first path connected to the first drain hole, and a second path connected to the second drain hole.

公开(公告)号：US10796767B2

公开(公告)日：2020-10-06

申请号：US16199098

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Minsu Kim ,  Hyun-Wook Park ,  Bongsoon Lim

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/04

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.

公开(公告)号：US09588568B2

公开(公告)日：2017-03-07

申请号：US13678858

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Chihyun Cho

IPC: G06F1/32 ,  G06F11/30

CPC classification number: G06F1/3206 ,  G06F1/3215 ,  G06F1/3265 ,  G06F1/3287 ,  G06F11/3003 ,  G06F11/3062 ,  G06F2201/865 ,  Y02D10/153 ,  Y02D50/20

Abstract: An electronic device and a method operative therein monitor automatic wakeup events that occur during a power save mode. Wakeup events are monitored for respective applications executable within the electronic device. Applications with processing activity during the power save mode are then listed, on the basis of at least the monitored wakeup events. An indication of which apps are consuming battery power during the power save mode can then be obtained.

Abstract translation: 一种在其中操作的电子设备和方法中，监视在节电模式期间发生的自动唤醒事件。 对在电子设备内可执行的相应应用来监视唤醒事件。 至少在监控的唤醒事件的基础上，列出了节能模式下具有处理活动的应用程序。 然后可以获得在省电模式期间哪些应用正在消耗电池电力的指示。

公开(公告)号：US12225303B2

公开(公告)日：2025-02-11

申请号：US18053184

申请日：2022-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Whoiyul Kim ,  Jeyeon Kim ,  Minsu Kim

IPC: H04N25/50 ,  G06T7/11 ,  G06T7/136 ,  G06T7/215 ,  G06T7/246 ,  H04N25/77

Abstract: A method of operating a dynamic vision sensor system includes: obtaining event signals from a plurality of dynamic vision sensor pixels over a predetermined time period, wherein the event signals correspond to a measured change in light; obtaining original image data based on the event signals output by the plurality of DVS pixels and including a plurality of image pixels, wherein the plurality of image pixels respectively correspond to the plurality of dynamic vision sensor pixels; obtaining binary image data by binarizing pixel values of the plurality of image pixels; defining a plurality of pixel groups from the plurality of image pixels in the binary image data; and selecting a plurality of effective groups from among the plurality of pixel groups that represent the movement of an object.

公开(公告)号：US11936384B2

公开(公告)日：2024-03-19

申请号：US18092507

申请日：2023-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/037 ,  G01R31/3185 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  G01R31/318541 ,  H03K3/037 ,  H03K3/35625

Abstract: A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.