公开(公告)号：US20200211663A1

公开(公告)日：2020-07-02

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10020314B1

公开(公告)日：2018-07-10

申请号：US15448409

申请日：2017-03-02

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Ching-Huang Lu ,  Yingda Dong

IPC: H01L21/336 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11526 ,  H01L27/11573

CPC classification number: H01L27/11519 ,  H01L21/823412 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

公开(公告)号：US20180175054A1

公开(公告)日：2018-06-21

申请号：US15891574

申请日：2018-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

公开(公告)号：US20180122814A1

公开(公告)日：2018-05-03

申请号：US15846620

申请日：2017-12-19

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yanli Zhang ,  Raghuveer Makala ,  Yingda Dong

IPC: H01L27/1157 ,  H01L27/105 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

公开(公告)号：US09779948B1

公开(公告)日：2017-10-03

申请号：US15185866

申请日：2016-06-17

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Ching-Huang Lu ,  Zhenyu Lu

IPC: H01L21/28 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/28282 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.

公开(公告)号：US11538828B2

公开(公告)日：2022-12-27

申请号：US16984920

申请日：2020-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L29/417 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556

Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

公开(公告)号：US11508748B2

公开(公告)日：2022-11-22

申请号：US16887818

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11543 ,  H01L27/11556 ,  H01L29/207 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11282857B2

公开(公告)日：2022-03-22

申请号：US16887738

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Peter Rabkin ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/207 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

公开(公告)号：US11101288B2

公开(公告)日：2021-08-24

申请号：US16710572

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Dong-il Moon ,  Raghuveer S. Makala ,  Peng Zhang ,  Wei Zhao ,  Ashish Baraskar

IPC: H01L27/11582 ,  H01L21/28 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US11037640B2

公开(公告)日：2021-06-15

申请号：US16900015

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.