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    Maintaining channel pre-charge in program operation
    24.
    发明授权
    Maintaining channel pre-charge in program operation 有权

    公开(公告)号：US10790003B1

    公开(公告)日：2020-09-29

    申请号：US16528349

    申请日：2019-07-31

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Wei Zhao

    IPC: G11C11/22 ,  G11C11/406

    Abstract: Techniques are described for maintaining a pre-charge voltage in a NAND string in a program operation. After a pre-charge voltage is applied to the channel of a NAND string, the word line voltages are controlled to avoid a large channel gradient which generates electron-hole pairs, where the electrons can pull down the channel boosting level on the drain side of the selected word line. In one approach, the word line voltages of a group of one or more source side word lines adjacent to the selected word line are increased directly from the level used during pre-charge to a pass voltage. The word line voltages of other source side word lines, and of drain side word lines, can be decreased and then increased to the pass voltage to provide a large voltage swing which couples up the channel.

    Memory device with charge isolation to reduce injection type of program disturb
    25.
    发明授权
    Memory device with charge isolation to reduce injection type of program disturb 有权

    公开(公告)号：US10593411B1

    公开(公告)日：2020-03-17

    申请号：US16281572

    申请日：2019-02-21

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Wei Zhao

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/28 ,  G11C7/10 ,  G11C11/56 ,  G11C7/04 ,  G11C16/32

    Abstract: Techniques are described for reducing an injection type of program disturb in a memory device. A charge isolation region is created in a channel of a NAND string on the source side of the selected word line, WLn, and spaced apart from WLn by one or more other word lines, when the program voltage is increased to a program voltage (Vpgm). The isolation region is created by applying 0 V or other low voltage to an isolation word line. The isolation region is maintained for a first portion of a time period in which Vpgm is applied. The charge isolation region can be modified based on factors associated with a risk of program disturb including the magnitude of Vpgm, the position of WLn in a set of word lines and an ambient temperature.

    Memory device with vpass step to reduce hot carrier injection type of program disturb
    26.
    发明授权
    Memory device with vpass step to reduce hot carrier injection type of program disturb 有权

    公开(公告)号：US10522232B2

    公开(公告)日：2019-12-31

    申请号：US15983365

    申请日：2018-05-18

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/34 ,  G11C16/10 ,  H01L27/11524 ,  G11C16/04 ,  H01L29/788 ,  G11C16/30

    Abstract: Apparatuses and techniques are described for reducing an injection type of program disturb in a memory device. A voltage on a selected word line is increased in a first step from an initial level such as 0 V to an intermediate, pass level such as Vpass, and in a second step from Vpass to a peak program level of Vpgm. A voltage on an adjacent unselected word line can be increased from the initial level to Vpass and then temporarily increased to an elevated level of Vpass_el during the second step increase on the selected word line. This helps reduce the magnitude of a channel gradient between the selected word line and the adjacent word line. The increase to Vpass_el may be implemented for program loops in the later part of a program operation, when Vpgm and the risk of program disturb is relatively high.

    Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify
    27.
    发明授权
    Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify 有权

    公开(公告)号：US10269435B1

    公开(公告)日：2019-04-23

    申请号：US15814769

    申请日：2017-11-16

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/26 ,  H01L27/11529

    Abstract: A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.

    Reducing injection type of read disturb in a cold read of a memory device
    28.
    发明授权
    Reducing injection type of read disturb in a cold read of a memory device 有权

    公开(公告)号：US10210941B1

    公开(公告)日：2019-02-19

    申请号：US15879084

    申请日：2018-01-24

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C16/10

    Abstract: A memory device and associated techniques for optimizing the channel boosting level in an unselected NAND string during a read operation for a selected NAND string. A tracking circuit tracks an indicator of a floating voltage of unselected word lines of a block. For example, this can include tracking a time since a last sensing operation, and determining whether a power on event has occurred without a subsequent sensing operation. In response to a read command, the indicator is used to set parameters in the read operation which can reduce disturbs. This can include setting a duration and/or a magnitude of a select gate voltage pulse during the increase of the voltage of the unselected word lines. The duration and/or a magnitude of the control gate voltage pulse can also be set based on a temperature.

    Program-verify of select gate transistor with doped channel in NAND string
    29.
    发明授权
    Program-verify of select gate transistor with doped channel in NAND string 有权

    公开(公告)号：US10153051B1

    公开(公告)日：2018-12-11

    申请号：US15879044

    申请日：2018-01-24

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Yingda Dong ,  Yen-Lung Li

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

    Abstract: A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.

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