Firmware assisted error handling scheme
    24.
    发明授权
    Firmware assisted error handling scheme 有权
    固件辅助错误处理方案

    公开(公告)号:US08448024B2

    公开(公告)日:2013-05-21

    申请号:US11804105

    申请日:2007-05-16

    IPC分类号: G06F11/00

    摘要: A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

    摘要翻译: 已经公开了计算机系统中的固件辅助错误处理方案。 在一个实施例中,响应于系统管理中断(SMI)陷阱,固件用于访问计算机系统内的一个或多个硬件特定的错误寄存器。 使用固件,构建一个常见错误记录格式的错误记录。 错误记录可用于计算机系统内的操作系统(OS)。

    Bi-directional handshake for advanced reliabilty availability and serviceability
    29.
    发明申请
    Bi-directional handshake for advanced reliabilty availability and serviceability 有权
    双向握手,提供可靠性和可维护性

    公开(公告)号:US20100332707A1

    公开(公告)日:2010-12-30

    申请号:US12459423

    申请日:2009-06-30

    申请人: Sarathy Jayakumar

    发明人: Sarathy Jayakumar

    IPC分类号: G06F13/00

    CPC分类号: G06F9/4411

    摘要: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

    摘要翻译: 在一些实施例中,信号从基本输入/输出系统发送到设备,以指示基本输入/输出系统需要获得对共享资源的控制。 信号从设备发送到基本输入/输出系统,指示基本输入/输出系统现在可以控制共享资源。 描述和要求保护其他实施例。

    Methods and apparatus for generating system management interrupts
    30.
    发明授权
    Methods and apparatus for generating system management interrupts 有权
    产生系统管理中断的方法和装置

    公开(公告)号:US07725637B2

    公开(公告)日:2010-05-25

    申请号:US11967299

    申请日:2007-12-31

    IPC分类号: G06F13/24

    CPC分类号: G06F9/4812

    摘要: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

    摘要翻译: 一种方法包括确定多个存储器地址,每个存储器地址彼此不同。 该方法还包括产生多个系统管理中断处理器中断,每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器,并且每个系统管理中断处理器中断包括多个存储器地址之一。 该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。 还公开了一种相关的机器可读介质。