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    Firmware assisted error handling scheme
    3.
    发明申请
    Firmware assisted error handling scheme 有权
    固件辅助错误处理方案

    公开(公告)号：US20080288815A1

    公开(公告)日：2008-11-20

    申请号：US11804105

    申请日：2007-05-16

    Applicant: Mohan Kumar ,  Sarathy Jayakumar

    Inventor： Mohan Kumar ,  Sarathy Jayakumar

    IPC: G06F11/07

    CPC classification number: G06F11/34 ,  G06F11/0706 ,  G06F11/0769

    Abstract: A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

    Abstract translation: 已经公开了计算机系统中的固件辅助错误处理方案。 在一个实施例中，响应于系统管理中断（SMI）陷阱，固件用于访问计算机系统内的一个或多个硬件特定的错误寄存器。 使用固件，构建一个常见错误记录格式的错误记录。 错误记录可用于计算机系统内的操作系统（OS）。

    FAST CACHE FLUSH
    4.
    发明申请
    FAST CACHE FLUSH 有权
    快速缓存

    公开(公告)号：US20150161037A1

    公开(公告)日：2015-06-11

    申请号：US14100721

    申请日：2013-12-09

    Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

    Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/7203

    Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in a volatile memory, determine whether the first data element is to be stored in a nonvolatile memory, and in response to a determination that the first data element is to be stored in a nonvolatile memory, to forward the first transaction to the memory controller coupled to the nonvolatile memory. Other examples are also disclosed and claimed.

    Abstract translation: 描述了管理存储器操作的装置，系统和方法。 在一个示例中，控制器包括接收第一事务以操作易失性存储器中的第一数据元素的逻辑，确定第一数据元素是否要存储在非易失性存储器中，并且响应于确定第一数据 元件将被存储在非易失性存储器中，以将第一事务转发到耦合到非易失性存储器的存储器控​​制器。 还公开并要求保护其他实例。

    SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS
    5.
    发明申请
    SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS 有权
    多核处理器的系统管理中断处理

    公开(公告)号：US20140281092A1

    公开(公告)日：2014-09-18

    申请号：US13799327

    申请日：2013-03-13

    Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

    Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

    IPC: G06F13/24

    CPC classification number: G06F9/4812 ,  G06F11/0772

    Abstract: Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

    Abstract translation: 用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。 进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。 其他处理器核心执行从属SMI处理程序。 主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。 响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。 进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。 描述和要求保护其他实施例。

    RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS
    6.
    发明申请
    RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS 有权
    INPUT / OUPUT ERROR-CONTAINENT事件后恢复

    公开(公告)号：US20130332781A1

    公开(公告)日：2013-12-12

    申请号：US13997870

    申请日：2012-06-06

    Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

    Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

    Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

    Abstract translation: 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

    FIRMWARE ASSISTED ERROR HANDLING SCHEME
    7.
    发明申请
    FIRMWARE ASSISTED ERROR HANDLING SCHEME 有权
    固件协助错误处理方案

    公开(公告)号：US20130254602A1

    公开(公告)日：2013-09-26

    申请号：US13891022

    申请日：2013-05-09

    Applicant: Mohan Kumar ,  Sarathy Jayakumar

    Inventor： Mohan Kumar ,  Sarathy Jayakumar

    IPC: G06F11/34

    CPC classification number: G06F11/34 ,  G06F11/0706 ,  G06F11/0769

    Abstract: A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

    Abstract translation: 已经公开了计算机系统中的固件辅助错误处理方案。 在一个实施例中，响应于系统管理中断（SMI）陷阱，固件用于访问计算机系统内的一个或多个硬件特定的错误寄存器。 使用固件，构建一个常见错误记录格式的错误记录。 错误记录可用于计算机系统内的操作系统（OS）。

    Memory Reconfiguration During System Run-Time
    9.
    发明申请
    Memory Reconfiguration During System Run-Time 有权
    系统运行时内存重新配置

    公开(公告)号：US20120079306A1

    公开(公告)日：2012-03-29

    申请号：US12890222

    申请日：2010-09-24

    Applicant: Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

    Inventor： Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

    IPC: G06F11/30 ,  G06F13/20

    CPC classification number: G06F11/3062 ,  G06F11/3031 ,  G06F11/3037 ,  G06F11/327

    Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

    Abstract translation: 描述系统运行时的内存重新配置。 在一个示例中，系统包括用于承载存储器板并且将存储器板连接到存储器控制器用于读取和写入操作的存储器插槽，具有多个状态寄存器以记录存储器槽的状态的逻辑设备和 多个控制寄存器来控制存储器插槽的操作，以及总线接口，通过直接信号线耦合到存储器插槽，以与存储器槽通信状态和控制信号，并通过串行总线耦合到逻辑器件以传送状态和 控制信号与逻辑器件。

    SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD
    10.
    发明申请
    SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD 有权

    公开(公告)号：US20210096848A1

    公开(公告)日：2021-04-01

    申请号：US17120072

    申请日：2020-12-11

    Applicant: Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

    Inventor： Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

    IPC: G06F8/656 ,  G06F9/48 ,  G06F9/4401 ,  G06F9/455 ,  G06F12/1027

    Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.

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