公开(公告)号：US5958069A

公开(公告)日：1999-09-28

申请号：US854741

申请日：1997-05-12

Applicant: Hiroya Kawasaki ,  Masaki Kira ,  Shiro Uriu ,  Yukinaga Toyoda ,  Kazumasa Sonoda

Inventor： Hiroya Kawasaki ,  Masaki Kira ,  Shiro Uriu ,  Yukinaga Toyoda ,  Kazumasa Sonoda

IPC: H04M3/22 ,  G06F11/20 ,  H04L29/14 ,  G06F11/16

CPC classification number: G06F11/2025 ,  G06F11/2038 ,  G06F11/2041

Abstract: A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device. The simplex unit executes predetermined control upon accepting control data from the apparent acting device.

Abstract translation: 系统包括作为作用装置和备用装置操作的主机，第一和第二装置以及由作用装置控制的单工装置。 每个设备设置有用于监视故障发生的监视单元，用于通知其他设备在其自己的设备中的故障的装置以及主动/备用通知装置。 主动/待机通知装置响应于来自主机的命令，当设备成为作用设备或备用设备时，通知单机设备本身正在行动或站立的设备。 当其他设备在其自身设备待机时发生故障时，主动/待机通知单元通知单机单元其自己的设备现在是表观动作设备。 当自己的设备在其自身的设备发生故障时，主动/备用通知装置通知单工装置其自己的设备现在是明显的待机设备。 单体单元在接受来自视在动作装置的控制数据时执行预定的控制。

公开(公告)号：US5448720A

公开(公告)日：1995-09-05

申请号：US940248

申请日：1992-09-04

Applicant: Shiro Uriu ,  Shuji Yoshimura ,  Yoshihiro Uchida

Inventor： Shiro Uriu ,  Shuji Yoshimura ,  Yoshihiro Uchida

IPC: G06F11/16 ,  G06F11/20 ,  H04B1/74 ,  H04J3/14 ,  H04M3/22 ,  H04Q3/545 ,  H04J1/16

CPC classification number: G06F11/2038 ,  G06F11/16 ,  G06F11/2028 ,  H04B1/74 ,  H04J3/14 ,  H04Q3/54558

Abstract: An information processing system includes a simplex system and a duplex system in which at least two data transmitting systems are provided each capable of being an act system or a standby system. Each data transmitting system has a data acquiring unit. The simplex system includes a controller for controlling a selector to switch between the systems. When in a standby condition, the data acquiring unit of the respective data transmitting system in the duplex system issues an access request signal to a switching signal generating unit provided in the controller of the simplex system to request that the output of the selector be switched from the act system to the standby system in the duplex system. Upon receipt of the access request signal from the data acquiring unit in the standby system, the switching signal generating unit switches the selector to the standby system. As a result, status data acquired by the data acquiring unit in the simplex section is output to the data acquiring section in the standby system. The duplex system uses the status data to make a diagnosis of the standby system for its normality.

Abstract translation: 信息处理系统包括单工系统和双工系统，其中提供至少两个能够作为动作系统或备用系统的数据传输系统。 每个数据发送系统具有数据获取单元。 单工系统包括用于控制选择器在系统之间切换的控制器。 当处于待机状态时，双工系统中的相应数据发送系统的数据获取单元向单工系统的控制器中提供的切换信号产生单元发出访问请求信号，以请求将选择器的输出从 该系统到双工系统中的备用系统。 在备用系统中从数据获取单元接收到访问请求信号时，切换信号生成单元将选择器切换到备用系统。 结果，将数据获取单元在单工部分中获取的状态数据输出到待机系统中的数据获取部分。 双工系统使用状态数据来对备用系统进行正常诊断。

公开(公告)号：US07194610B2

公开(公告)日：2007-03-20

申请号：US11063860

申请日：2005-02-23

Applicant: Shiro Uriu ,  Mitsuharu Wakayoshi ,  Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki

Inventor： Shiro Uriu ,  Mitsuharu Wakayoshi ,  Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki

IPC: G06F13/00

CPC classification number: G06F15/7867 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3897

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract translation: 可重配置处理器从硬件配置信息计算执行流水线处理的配置执行时间，并修复时钟周期，直到处理结束为止。 计数器将固定时钟周期与实际经过的时钟数进行比较，当经过的时钟数等于时钟周期时，确定流水线处理已经结束，并且通知配置控制器。

公开(公告)号：US20060010306A1

公开(公告)日：2006-01-12

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US20060004993A1

公开(公告)日：2006-01-05

申请号：US11063860

申请日：2005-02-23

Applicant: Shiro Uriu ,  Mitsuharu Wakayoshi ,  Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki

Inventor： Shiro Uriu ,  Mitsuharu Wakayoshi ,  Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki

IPC: G06F9/00

CPC classification number: G06F15/7867 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3897

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract translation: 可重构处理器根据硬件配置信息计算执行流水线处理的配置执行时间，并修复时钟周期，直到处理结束为止。 计数器将固定时钟周期与实际经过的时钟数进行比较，当经过的时钟数等于时钟周期时，确定流水线处理已经结束，并且通知配置控制器。

公开(公告)号：US5875177A

公开(公告)日：1999-02-23

申请号：US957387

申请日：1997-10-23

Applicant: Shiro Uriu ,  Yoshihiro Uchida ,  Shuji Yoshimura

Inventor： Shiro Uriu ,  Yoshihiro Uchida ,  Shuji Yoshimura

IPC: H04J3/14 ,  H04L12/26 ,  H04L12/28 ,  H04L12/70 ,  H04Q11/04

CPC classification number: H04J3/14 ,  H04Q11/0478 ,  H04L2012/5628

Abstract: A sending trunk on the input side of an ATM switch is equipped with a test cell generating section, and a receiving trunk on the output side of the ATM switch is equipped with a test cell detecting section. The test cell generating section includes a unit for setting a test cell identifier in the header of a test cell and a unit for generating pieces of data with regularity in the information field of the test cell. The test cell detecting section includes a unit for detecting the test cell identifier from the header of a cell received and a unit for detecting regularity from data in the information field of the cell received. When a test cell is transmitted, the test cell detecting section evaluates the result of a test on the basis of the result of detection of the test cell identifier from the header of the test cell and the result of detection of the regularity from data in the information field of the test cell.

Abstract translation: 在ATM交换机的输入侧的发送中继装置具有测试小区生成部分，ATM交换机的输出侧的接收中继装备有测试小区检测部分。 测试小区生成部分包括用于在测试小区的头部中设置测试小区标识符的单元和用于在测试小区的信息字段中规则地生成数据片段的单元。 测试小区检测部分包括从接收的小区的头部检测测试小区标识符的单元和用于从所接收的小区的信息字段中的数据检测规则性的单元。 当测试单元被发送时，测试单元检测部分根据测试单元标识符的检测结果和来自测试单元的标题的规则性的检测结果来评估测试结果 测试单元的信息字段。

公开(公告)号：US5345451A

公开(公告)日：1994-09-06

申请号：US848170

申请日：1992-03-10

Applicant: Shiro Uriu ,  Shuji Yoshimura

Inventor： Shiro Uriu ,  Shuji Yoshimura

IPC: H04L7/00 ,  H03M13/00 ,  H04L1/00 ,  H04L7/04 ,  H04L12/70 ,  H04Q11/04 ,  G06F11/10

CPC classification number: H04L1/0061 ,  H04L1/0052 ,  H04L1/0072 ,  H04L7/048 ,  H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5674

Abstract: A CRC operating unit which performs a CRC operation on received data using as an initial value a CRC operation result actual value obtained in a previous operation, and outputs a CRC operation result actual value. A delay unit delays the CRC operation result actual value by the time taken for a header part to be entered. The CRC operation result derivation unit outputs as a CRC operation result derivation value an operation result obtained by a CRC operation performed for all the receiving data of a header part provided with the above described CRC code using the CRC operation result actual value as an initial value. The coincidence detecting unit compares the CRC operation result actual value with the CRC operation result derivation value to detect the input timing of a header part as coincident timing for both values.

Abstract translation: CRC操作单元，其使用在先前操作中获得的CRC运算结果实际值作为初始值对接收到的数据执行CRC操作，并输出CRC运算结果实际值。 延迟单元将CRC运算结果实际值延迟到输入标题部分所花费的时间。 CRC运算结果导出部将CRC运算结果导出值作为初始值输出作为CRC运算结果导出值的运算结果，该运算结果通过对具有上述CRC码的头部部分的所有接收数据执行的CRC运算获得， 。 一致检测单元将CRC运算结果实际值与CRC运算结果推导值进行比较，以检测报头部分的输入定时为两个值的重合定时。

公开(公告)号：US07774580B2

公开(公告)日：2010-08-10

申请号：US11077561

申请日：2005-03-11

Applicant: Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

Inventor： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F15/8007

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract translation: 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

公开(公告)号：US06789176B2

公开(公告)日：2004-09-07

申请号：US09286332

申请日：1999-04-05

Applicant: Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

Inventor： Shiro Uriu ,  Masanobu Furukoshi ,  Tetsuaki Wakabayashi ,  Kazumasa Sonoda

IPC: G06F1206

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/5681

Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Abstract translation: 在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。 对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。 然后，释放相关的写入地址。 在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。 每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。 当行匹配时，释放写入控制表中设置的ATM信元的写入地址。

公开(公告)号：US07453800B2

公开(公告)日：2008-11-18

申请号：US10020077

申请日：2001-10-30

Applicant: Ryo Takajitsuko ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroya Kawasaki

Inventor： Ryo Takajitsuko ,  Kenichi Okabe ,  Shiro Uriu ,  Hiroya Kawasaki

IPC: H04L12/56

CPC classification number: H04L49/3081 ,  H04L49/1523 ,  H04L49/30 ,  H04L49/506 ,  H04L2012/5635

Abstract: A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.

Abstract translation: 用于在不同接口之间切换的通信装置包括开关单元。 开关单元包括用于切换固定长度的数据的主开关和具有用于主开关的输入的第一缓冲器和用于主开关的输出的第二缓冲器的接口。