公开(公告)号：US20190006393A1

公开(公告)日：2019-01-03

申请号：US16039869

申请日：2018-07-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kenichi OKAZAKI ,  Masahiko HAYAKAWA ,  Shinpei MATSUDA

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1368

Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.

公开(公告)号：US20180315780A1

公开(公告)日：2018-11-01

申请号：US16026115

申请日：2018-07-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L33/62 ,  H01L27/06 ,  G09G3/3275 ,  G09G3/3233 ,  H01L27/32

CPC classification number: H01L27/1225 ,  G09G3/3233 ,  G09G3/3275 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/045 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3241 ,  H01L33/62

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

公开(公告)号：US20180174543A1

公开(公告)日：2018-06-21

申请号：US15852669

申请日：2017-12-22

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Hiroyuki MIYAKE

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2300/0814 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287

Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

公开(公告)号：US20180026053A1

公开(公告)日：2018-01-25

申请号：US15677125

申请日：2017-08-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Hideaki SHISHIDO ,  Jun KOYAMA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode. The second light-transmitting conductive film is formed over the same surface as the light-transmitting semiconductor film of the transistor and is a metal oxide film containing a dopant.

公开(公告)号：US20170352318A1

公开(公告)日：2017-12-07

申请号：US15685273

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: G09G3/36 ,  G06F3/044 ,  G06F3/041 ,  G06F3/042 ,  G02F1/1345

CPC classification number: G09G3/3618 ,  G02F1/1345 ,  G06F3/0416 ,  G06F3/0421 ,  G06F3/044 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/04 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2320/10 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/16 ,  G09G2354/00

Abstract: The liquid crystal display device includes a first substrate provided with a terminal portion, a switching transistor, a driver circuit portion, and a pixel circuit portion including a pixel transistor and a plurality of pixels, a second substrate provided with a common electrode electrically connected to the terminal portion through the switching transistor, and liquid crystal between a pixel electrode and the common electrode. In a period during which a still image is switched to a moving image, the following steps are sequentially performed: a first step of supplying the common potential to the common electrode; a second step of supplying a power supply voltage to the driver circuit portion; a third step of supplying a clock signal to the driver circuit portion; and a fourth step of supplying a start pulse signal to the driver circuit portion.

公开(公告)号：US20170278876A1

公开(公告)日：2017-09-28

申请号：US15621432

申请日：2017-06-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Hiroyuki MIYAKE ,  Hidekazu MIYAIRI

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/3291

CPC classification number: H01L27/1225 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/04

Abstract: To provide a semiconductor device including a small-area circuit with high withstand voltage, an oxide semiconductor (OS) transistor is used as some of transistors included in a circuit handling an analog signal in a circuit to which high voltage is applied. The use of an OS transistor with high withstand voltage as a transistor requiring resistance to high voltage enables the circuit area to be reduced without lowering the performance, as compared to the case using a Si transistor. Furthermore, an OS transistor can be provided over a Si transistor, so that transistors using different semiconductor layers can be stacked, resulting in a much smaller circuit area.

公开(公告)号：US20170271378A1

公开(公告)日：2017-09-21

申请号：US15451540

申请日：2017-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kenichi OKAZAKI ,  Hiroyuki MIYAKE ,  Kengo AKIMOTO ,  Masami JINTYOU ,  Takahiro IGUCHI

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1229 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/3262 ,  H01L29/045 ,  H01L29/24 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a reduced layout area of transistors is provided. The semiconductor device includes a first transistor including a first oxide semiconductor film and a second transistor including a second oxide semiconductor film over a substrate. When the oxide semiconductor films are subjected to electron diffraction, the ratio of the integrated intensity of luminance of a diffraction spot derived from c-axis alignment to the integrated intensity of luminance of a diffraction spot derived from alignment in any direction in the first oxide semiconductor film is higher than that in the second oxide semiconductor film. In addition, part of the first transistor is located between the second transistor and the substrate.

公开(公告)号：US20170229488A1

公开(公告)日：2017-08-10

申请号：US15494833

申请日：2017-04-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G02F2202/10 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/7869

Abstract: To provide a display device including a transistor that includes an oxide semiconductor and has favorable characteristics, a pixel electrode electrically connected to the transistor, and a capacitor electrically connected to the pixel electrode. To provide a display device that can be manufactured at low cost. The display device includes a display element including a pixel electrode, a transistor that performs switching of the display element and includes a first oxide semiconductor layer serving as a channel formation region, a capacitor that is electrically connected to the display element and includes a dielectric layer between a pair of electrodes. The pixel electrode is a second oxide semiconductor layer formed on the same surface as that on which the first oxide semiconductor layer is formed, and also serves as one electrode of the capacitor.

公开(公告)号：US20170162159A1

公开(公告)日：2017-06-08

申请号：US15433629

申请日：2017-02-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki MIYAKE

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G09G2300/0814 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287

Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

公开(公告)号：US20170104013A1

公开(公告)日：2017-04-13

申请号：US15385157

申请日：2016-12-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE ,  Junichi KOEZUKA ,  Masami JINTYOU ,  Yukinori SHIMA ,  Shunpei YAMAZAKI

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/7869

Abstract: A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits. The first circuit has a function of generating a signal including a value of current extracted from the pixel. The second circuit has a function of correcting an image signal by the signal. The pixel includes at least a light-emitting element and first and second transistors. The first transistor has a function of controlling supply of the current to the light-emitting element by the image signal. The second transistor has a function of controlling extraction of the current from the pixel. A semiconductor film of each of the first and second transistors includes a first semiconductor region overlapping with a gate, a second semiconductor region in contact with a source or a drain, and a third semiconductor region between the first and second semiconductor regions.