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    ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME
    21.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME 审中-公开

    公开(公告)号：US20200058678A1

    公开(公告)日：2020-02-20

    申请号：US16343024

    申请日：2017-10-12

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

    IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L27/02 ,  G02F1/1368 ,  G02F1/1362

    Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode. The conductive layer (25) does not include any of the pixel electrode, the common electrode, and the auxiliary capacitor electrode, and does not have a Ti layer being in contact with the Cu layer (15b) of the gate metal layer (15).

    ACTIVE MATRIX SUBSTRATE
    24.
    发明公开
    ACTIVE MATRIX SUBSTRATE 审中-公开

    公开(公告)号：US20240297181A1

    公开(公告)日：2024-09-05

    申请号：US18663479

    申请日：2024-05-14

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

    IPC: H01L27/12 ,  H01L29/786

    CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/7869 ,  H01L29/78696

    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
    26.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME 有权

    公开(公告)号：US20210249445A1

    公开(公告)日：2021-08-12

    申请号：US17156769

    申请日：2021-01-25

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

    IPC: H01L27/12 ,  H01L29/786

    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

    SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
    27.
    发明申请
    SEMICONDUCTOR DEVICE AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20200227560A1

    公开(公告)日：2020-07-16

    申请号：US16491248

    申请日：2018-03-01

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Toshikatsu ITOH ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Masahiko SUZUKI

    IPC: H01L29/786 ,  H01L27/12

    Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 μm.

    METHOD OF PRODUCING DISPLAY PANEL BOARD
    28.
    发明申请
    METHOD OF PRODUCING DISPLAY PANEL BOARD 审中-公开

    公开(公告)号：US20190079364A1

    公开(公告)日：2019-03-14

    申请号：US16124223

    申请日：2018-09-07

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Masaki MAEDA ,  Hideki KITAGAWA ,  Toshikatsu ITOH ,  Tatsuya KAWASAKI

    IPC: G02F1/1362 ,  H01L33/42 ,  H01L21/477 ,  H01L21/02 ,  H01L33/00 ,  H01L33/28

    Abstract: A method includes a pixel electrode forming process of forming a pixel electrode formed from a transparent electrode film on a gate insulation film that covers a gate electrode, a semiconductor film forming process being performed after the pixel electrode forming process and forming a semiconductor film on the gate insulation film such that a part of the semiconductor film covers the pixel electrode, an annealing process being performed after the semiconductor film forming process and processing the semiconductor film with annealing, and an etching process being performed after the annealing process and processing the semiconductor film with etching such that a channel section overlapping the gate electrode is formed in a same layer as the pixel electrode. The etching and the annealing performed on one of the transparent electrode film and the semiconductor film is less likely to adversely affect another one of the films.

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