公开(公告)号：US07358107B2

公开(公告)日：2008-04-15

申请号：US11260955

申请日：2005-10-27

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas J. Tweet

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu ,  Douglas J. Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1808 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02647 ,  H01L31/105 ,  Y02E10/50

摘要： A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and in the contact holes; growing an intrinsic germanium layer on the epitaxial germanium layer and any exposed silicon oxide layer; growing a germanium layer of a second type on the intrinsic germanium layer and any exposed silicon oxide layer; depositing a layer of covering material take from the group of materials consisting of polysilicon, polysilicon-germanium and In2O3—SnO2; and etching the covering material to form individual sensing elements.

摘要翻译： 制造锗光电检测器的方法包括制备硅衬底; 沉积和平坦化氧化硅层; 在氧化硅层中形成与底层硅衬底连通的接触孔; 在氧化硅层和接触孔中生长第一类型的外延锗层; 在外延锗层和任何暴露的氧化硅层上生长内在的锗层; 在内部锗层和任何暴露的氧化硅层上生长第二类型的锗层; 沉积一层覆盖材料取自由多晶硅，多晶硅 - 锗和In 2 N 3 O 3 -SnO 2 2组成的材料组。 并蚀刻覆盖材料以形成单独的感测元件。

公开(公告)号：US07247545B2

公开(公告)日：2007-07-24

申请号：US10985444

申请日：2004-11-10

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing a counter wafer; bonding the germanium thin film to a counter wafer to form a bonded structure; annealing the bonded structure at a temperature of at least 375° C. to facilitate splitting of the bonded wafer; splitting the bonded structure to expose the germanium thin film; removing any remaining silicon from the germanium thin film surface along with a portion of the germanium thin film defect zone; and incorporating the low-defect germanium thin film into the desired end-product device.

摘要翻译： 制造低缺陷锗薄膜的方法包括制备用于锗沉积的硅晶片; 使用两步CVD工艺形成锗膜，使用多循环工艺退火锗薄膜; 植入氢离子; 沉积和平滑一层四乙基原硅酸盐氧化物（TEOS）; 准备一个反晶圆; 将锗薄膜结合到对置晶片上以形成结合结构; 在至少375℃的温度下对接合结构进行退火以促进键合晶片的分裂; 分离粘结结构以暴露锗薄膜; 从锗薄膜表面除去锗薄膜缺陷区的一部分剩余的硅; 并将低缺陷锗薄膜并入期望的最终产品装置中。

公开(公告)号：US07138309B2

公开(公告)日：2006-11-21

申请号：US11039542

申请日：2005-01-19

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.

摘要翻译： 制造用于NMOS制造的双轴拉伸应变层的方法和用于CMOS IC的单个晶片上的用于PMOS制造的单轴压缩应变层包括制备用于CMOS制造的硅衬底; 沉积，图案化和蚀刻第一和第二绝缘层; 从PMOS有源区域去除所述第二绝缘层的一部分; 在PMOS有源区上沉积一层外延硅; 从NMOS有源区域去除所述第二绝缘层的一部分; 生长外延硅层并在NMOS有源区上生长外延SiGe层; 注入H 2 O 2 + + / - +离子; 退火晶片以松弛SiGe层; 从晶片上去除剩余的第二绝缘层; 生长一层硅; 完成门模块; 沉积SiO 2层以覆盖NMOS晶片; 蚀刻PMOS有源区中的硅; 在PMOS有源区上选择性地生长SiGe层; 其中所述NMOS有源区中的硅层处于双轴拉伸应变下，并且所述PMOS有源区中的硅层是单轴压缩应变的; 并完成CMOS设备。

公开(公告)号：US07071042B1

公开(公告)日：2006-07-04

申请号：US11073163

申请日：2005-03-03

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet

IPC分类号： H01L21/84

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L29/78603 ,  H01L29/78606

摘要： A method of fabricating a silicon integrated circuit on a glass substrate includes preparing a glass substrate; fabricating a silicon layer on the glass substrate; implanting ions into the active areas of the silicon layer; covering the silicon layer with a heat pad material; activating the ions in the silicon layer by annealing while maintaining the glass substrate at a temperature below that of the thermal stability of the glass substrate; removing the heat pad material; and completing the silicon integrated circuit.

摘要翻译： 在玻璃基板上制造硅集成电路的方法包括制备玻璃基板; 在玻璃基板上制造硅层; 将离子注入硅层的有源区; 用加热垫材料覆盖硅层; 通过退火激活硅层中的离子，同时将玻璃基板保持在低于玻璃基板的热稳定性的温度; 去除热垫材料; 并完成硅集成电路。

公开(公告)号：US06992025B2

公开(公告)日：2006-01-31

申请号：US10755615

申请日：2004-01-12

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/26 ,  H01L21/42 ,  H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了一种包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

公开(公告)号：US06780796B2

公开(公告)日：2004-08-24

申请号：US10625015

申请日：2003-07-22

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21324

CPC分类号： H01L21/322 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

公开(公告)号：US06703293B2

公开(公告)日：2004-03-09

申请号：US10194383

申请日：2002-07-11

申请人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

发明人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

IPC分类号： H01L21265

CPC分类号： H01L21/02381 ,  C30B25/02 ,  C30B29/52 ,  C30B31/22 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

摘要翻译： 在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在大于Tc的温度下使Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

公开(公告)号：US07906825B2

公开(公告)日：2011-03-15

申请号：US12630893

申请日：2009-12-04

申请人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L27/14

CPC分类号： H01L31/1055 ,  H01L27/14643 ,  H01L27/14689

摘要： A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.

摘要翻译： 提供锗（Ge）短波长红外（SWIR）成像器和相关制造工艺。 该成像器包括具有掺杂阱的硅（Si）衬底。 在位于Si衬底上的松弛的含Ge膜中形成一个pin二极管阵列，每个pin二极管具有倒装芯片接口。 存在Ge / Si界面和插入含Ge膜和Ge / Si界面之间的含掺杂Ge的缓冲层。 Si CMOS读出电路阵列结合到倒装芯片接口。 每个读出电路都具有零伏二极管偏置接口。

公开(公告)号：US07786469B2

公开(公告)日：2010-08-31

申请号：US12236480

申请日：2008-09-23

申请人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L31/00

CPC分类号： H01L31/035254 ,  B82Y20/00 ,  H01L27/14649 ,  H01L31/028 ,  H01L31/101 ,  H01L31/1804 ,  Y02P70/521

摘要： A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

摘要翻译： 硅/锗（SiGe）超晶格热传感器具有相应的制造方法。 该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。 第一基板与第二基板接合，形成接合基板。 在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。

公开(公告)号：US07390725B2

公开(公告)日：2008-06-24

申请号：US11284326

申请日：2005-11-21

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/46 ,  H01L21/30

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。