公开(公告)号：US07390725B2

公开(公告)日：2008-06-24

申请号：US11284326

申请日：2005-11-21

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/46 ,  H01L21/30

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

公开(公告)号：US06992025B2

公开(公告)日：2006-01-31

申请号：US10755615

申请日：2004-01-12

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/26 ,  H01L21/42 ,  H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了一种包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

公开(公告)号：US07361574B1

公开(公告)日：2008-04-22

申请号：US11601173

申请日：2006-11-17

申请人： Jer-Shen Maa ,  David R. Evans ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  David R. Evans ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/30 ,  H01L21/461

CPC分类号： H01L21/76251 ,  H01L21/84 ,  Y10S438/926 ,  Y10S438/933

摘要： A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.

摘要翻译： 提供了将单晶硅（Si）膜转印到玻璃基板上的方法。 该方法沉积覆盖Si晶片的含锗（Ge）的材料，形成牺牲含Ge膜。 形成覆盖牺牲的含Ge膜的单晶Si膜。 将Si膜表面粘合到透明基板上，形成键合衬底。 将键合衬底浸入Ge蚀刻溶液中以除去将透明衬底与Si晶片分离的牺牲Ge含量膜。 结果是具有上覆单晶Si膜的透明衬底。 可选地，可以形成通道以分布Ge蚀刻溶液，并促进除去含Ge膜。

公开(公告)号：US07241670B2

公开(公告)日：2007-07-10

申请号：US10936400

申请日：2004-09-07

申请人： Douglas J. Tweet ,  David R. Evans ,  Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Douglas J. Tweet ,  David R. Evans ,  Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/1054 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

摘要翻译： 在半导体器件中形成具有高锗含量的弛豫SiGe层的方法包括制备硅衬底; 沉积应变SiGe层; 将离子注入到应变SiGe层中，其中离子包括选自由硼和氦构成的离子组的硅离子和离子，并且还包括注入H +离子; 退火以使应变SiGe层松弛，从而形成第一弛豫SiGe层; 并完成半导体器件。

公开(公告)号：US07405098B2

公开(公告)日：2008-07-29

申请号：US11339017

申请日：2006-01-25

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  David R. Evans ,  Allen Burmaster

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  David R. Evans ,  Allen Burmaster

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/76 ,  H01L21/20 ,  H01L21/36

CPC分类号： C30B19/00 ,  C30B29/08 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02623 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/7624 ,  H01L27/14683 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/78 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1126 ,  H01L31/1136 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

摘要： A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.

摘要翻译： 提供一种形成具有光滑表面的液相外延（LPE）锗（Ge） - 绝缘体（GOI）薄膜的方法。 该方法提供硅（Si）晶片，形成覆盖Si晶片的氮化硅绝缘体层，并且选择性地蚀刻氮化硅绝缘体层，形成Si种子接入区域。 然后，该方法共同沉积覆盖氮化硅绝缘体层和Si种子访问区域的Ge，形成具有第一表面粗糙度的Ge层，并且使用化学机械抛光（CMP）工艺平滑Ge层。 通常，该方法封装Ge层并退火Ge层以形成LPE Ge层。 Ge层形成有小于第一表面粗糙度的第二表面粗糙度。 在某些方面，该方法在LPE Ge层中形成有源器件。

公开(公告)号：US06303502B1

公开(公告)日：2001-10-16

申请号：US09588940

申请日：2000-06-06

申请人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L2144

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.

摘要翻译： 制造单晶体管存储器的方法包括在单晶硅衬底上，在栅氧化层上沉积底电极结构; 注入离子以形成源极区域和漏极区域并激活注入的离子旋转涂覆第一铁电层的结构; 沉积第二铁电层; 并退火该结构以提供c轴铁电取向。

公开(公告)号：US06777327B2

公开(公告)日：2004-08-17

申请号：US09820068

申请日：2001-03-28

申请人： Wei Pan ,  Jer-Shen Maa ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Jer-Shen Maa ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  C23C16/0209 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76864 ,  H01L21/76876

摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.

摘要翻译： 快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤 在非反应性气体如氢气（H 2），氩气（Ar）或氦气（He））或在环境真空中，在250-550摄氏度的温度范围内。 室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。 在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。 预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。 因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

公开(公告)号：US06627510B1

公开(公告)日：2003-09-30

申请号：US10112014

申请日：2002-03-29

申请人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

发明人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

IPC分类号： H01L21762

CPC分类号： H01L21/28194 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/975

摘要： A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.

摘要翻译： 提供了一种改进的STI工艺，包括在衬底上形成第一多晶硅层。 通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。 在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部 层。 然后可以使用CMP工艺将得到的结构平坦化。 可以通过选择性地蚀刻氧化物层来形成对准键。 然后可以使用光致抗蚀剂沉积和图案化第三多晶硅层以形成栅极结构。 在图案化期间，蚀刻暴露的第二多晶硅层。 在完成去除第二多晶硅层时检测到蚀刻停止。 保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。

公开(公告)号：US07364989B2

公开(公告)日：2008-04-29

申请号：US11174350

申请日：2005-07-01

申请人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

公开(公告)号：US06716691B1

公开(公告)日：2004-04-06

申请号：US10606105

申请日：2003-06-25

申请人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

发明人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L21/823878

摘要： A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.

摘要翻译： 制造CMOS的方法具有自对准浅沟槽隔离，包括制备硅衬底; 形成栅极叠层; 沉积第一多晶硅层; 通过浅沟槽隔离对衬底进行沟槽以形成沟槽; 用氧化物填充沟槽; 沉积第二多晶硅层，其中第二多晶硅层的顶表面在第一多晶硅层的顶表面之上; 沉积厚度至少为第一多晶硅层的1.5倍的牺牲氧化物层; 将牺牲氧化物层CMP CMP化为第二多晶硅层的上表面的水平; 沉积第三层多晶硅; 图案化和蚀刻栅极堆叠; 注入离子以形成源极区，漏极区和多晶硅栅; 并完成CMOS结构。