公开(公告)号：US06649957B2

公开(公告)日：2003-11-18

申请号：US10345725

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

IPC分类号： H01L2976

CPC分类号： H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

摘要翻译： 描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层 绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。 还描述了形成多晶存储器结构的方法。 沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。 绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

公开(公告)号：US06534326B1

公开(公告)日：2003-03-18

申请号：US10099186

申请日：2002-03-13

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei-Wei Zhuang

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.

摘要翻译： 描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层 绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。 还描述了形成多晶存储器结构的方法。 沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。 绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

公开(公告)号：US06462366B1

公开(公告)日：2002-10-08

申请号：US09481674

申请日：2000-01-12

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2976

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of &dgr;, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2&dgr;; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2≧L1+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对所述结构进行金属化。铁电存储晶体管包括其中形成有p阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta，其中Δ是光刻工艺的对准公差。

公开(公告)号：US06849891B1

公开(公告)日：2005-02-01

申请号：US10730584

申请日：2003-12-08

申请人： Sheng Teng Hsu ,  Wei Pan ,  Fengyan Zhang ,  Wei-Wei Zhuang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Wei Pan ,  Fengyan Zhang ,  Wei-Wei Zhuang ,  Tingkai Li

IPC分类号： H01L21/28 ,  G11C13/00 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/22 ,  H01L29/68 ,  H01L39/00 ,  H01L43/08 ,  H01L45/00 ,  H01L29/94

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1675

摘要： A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.

摘要翻译： 在其上具有工作结的硅衬底上形成有一个RRAM存储单元和形成在其上的金属插塞，包括第一氧化电阻层; 第一难熔金属层; 一个CMR层; 第二难熔金属层; 和第二氧化电阻层。 制造多层电极RRAM存储单元的方法包括制备硅衬底; 从由N +结和P +结组成的接头组中形成在衬底中的结; 在接头上沉积金属塞; 在金属插塞上沉积第一抗氧化层; 在第一耐氧化层上沉积第一难熔金属层; 在第一难熔金属层上沉积CMR层; 在CMR层上沉积第二难熔金属层; 在所述第二难熔金属层上沉积第二抗氧化层; 并完成RRAM存储单元。

公开(公告)号：US06590243B2

公开(公告)日：2003-07-08

申请号：US09301434

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2976

CPC分类号： H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

公开(公告)号：US06531325B1

公开(公告)日：2003-03-11

申请号：US10164785

申请日：2002-06-04

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2100

CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/11502 ,  H01L29/78391

摘要： A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack. A method of forming a ferroelectric memory transistor includes preparing a substrate, including forming active regions and an oxide device isolation region; forming a gate placeholder structure in a gate region; removing the gate placeholder structure forming a gate void in the gate region; depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup; filling the high-k cup with a ferroelectric material to form a ferroelectric element; depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element; depositing a top electrode over the high-k cap to form a gate electrode and gate stack; depositing a layer of passivation oxide over the structure; etching the passivation oxide to from contact vias to the active regions and the gate stack; and metallizing the structure to complete the ferroelectric memory transistor.

摘要翻译： 铁电存储晶体管包括其中具有有源区的衬底; 包括：高k绝缘体元件，包括高k杯和高k帽; 铁电元件，其中所述铁电元件封装在所述高k绝缘体元件内; 以及位于所述高k绝缘体的顶部上的顶电极; 位于衬底和栅极叠层上方的钝化氧化物层; 以及金属化以形成与有源区和栅叠层的接触。 形成铁电存储晶体管的方法包括：制备基片，包括形成有源区和氧化物器件隔离区; 在栅极区域形成栅极占位符结构; 去除在栅极区域中形成栅极空隙的栅极占位符结构; 在结构上和栅极空隙中沉积高k绝缘体层以从高k杯沉积; 用铁电材料填充高k杯以形成铁电元件; 沉积高k上绝缘体层并去除多余的高k材料以在铁电元件上形成高k帽; 在顶部电极上沉​​积高k帽以形成栅电极和栅叠层; 在结构上沉积一层钝化氧化物; 将钝化氧化物从接触孔蚀刻到有源区和栅叠层; 并且对结构进行金属化以完成铁电存储晶体管。

公开(公告)号：US06457479B1

公开(公告)日：2002-10-01

申请号：US09965581

申请日：2001-09-26

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Sheng Teng Hsu ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Sheng Teng Hsu ,  Tingkai Li

IPC分类号： B08B600

CPC分类号： H01L21/02071 ,  B08B3/12 ,  Y10S134/902

摘要： A method of cleaning a metal oxide thin film on a silicon wafer, includes dipping the wafer in an organic solvent; drying the wafer in a nitrogen atmosphere; and stripping any photoresist from the wafer in an oxygen atmosphere under partial vacuum at a temperature of about 200° C. The wafer may also be cleaned by dipping in a polar organic solvent and subjecting the wafer to ultrasound while immersed in the solvent.

摘要翻译： 一种在硅晶片上清洗金属氧化物薄膜的方法，包括将晶片浸入有机溶剂中; 在氮气气氛中干燥晶片; 并且在约200℃的温度下，在部分真空下，在氧气氛中从晶片上剥离任何光致抗蚀剂。也可以通过浸渍在极性有机溶剂中并将晶片浸入溶剂中使其超声波清洗晶片。

公开(公告)号：US06420740B1

公开(公告)日：2002-07-16

申请号：US09317780

申请日：1999-05-24

申请人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L2976

CPC分类号： H01L28/56 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/75

摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD caxis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.

摘要翻译： 提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。 该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。 在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。 通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD caxis取向铅酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。 因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。 还提供了形成上述多层电极铁电体结构体的方法。

公开(公告)号：US06281022B1

公开(公告)日：2001-08-28

申请号：US09704496

申请日：2000-11-01

申请人： Tingkai Li ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31691 ,  C23C16/40 ,  C23C16/56 ,  H01L21/31604 ,  H01L28/55

摘要： A MOCVD deposition process has been provided for the deposition of an improved PGO ferroelectric film. The inclusion of a second phase of Pb3GeO5, along with the first phase of Pb5Ge3O11, provides the film with some ferroelastic properties which direct correspond to improved ferroelectric characteristics. The inclusion of the second phase regulates to first phase crystal grain size and promotes the preferred c-axis orientation of the grains. The degree of second phase Pb3GeO5 is regulated by controlling the amount of lead in the precursor, and with additional lead added to the reactor along the oxygen used to oxidize the lead-germanium film. Critical post-deposition annealing process are also described which optimize the ferroelectric properties of the PGO film. A multi-phase PGO film and capacitor structure including multi-phase PGO film of the present invention are provided by means of the invention.

摘要翻译： 已经提供了用于沉积改进的PGO铁电体膜的MOCVD沉积工艺。 包含Pb3GeO5的第二相以及Pb5Ge3O11的第一相为膜提供一些直接对应于改进的铁电特性的铁弹性质。 第二相的包含调节到第一相晶粒尺寸并且促进晶粒的优选的c轴取向。 第二相Pb3GeO5的程度是通过控制前体中的铅的量来调节的，并且沿着用于氧化铅 - 锗膜的氧加入到反应器中的另外的铅被调节。 还描述了优化PGO膜的铁电性能的关键后沉积退火工艺。 本发明提供了包括本发明多相PGO膜的多相PGO膜和电容器结构。

公开(公告)号：US07645669B2

公开(公告)日：2010-01-12

申请号：US11707712

申请日：2007-02-16

申请人： Sheng Teng Hsu ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/94 ,  B82Y10/00 ,  H01L28/91 ,  H01L29/66083

摘要： A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.

摘要翻译： 提供了一种纳米尖端电容器和相关联的制造方法。 该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。 沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。 通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。 在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。 然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。