公开(公告)号：US4837748A

公开(公告)日：1989-06-06

申请号：US38107

申请日：1987-04-14

Applicant: Shine C. Chung ,  Siu K. Tsang ,  James T. Koo ,  Sho Long S. Chen ,  John Y. Chan

Inventor： Shine C. Chung ,  Siu K. Tsang ,  James T. Koo ,  Sho Long S. Chen ,  John Y. Chan

IPC: G11C8/00 ,  G11C8/04 ,  G11C16/10

CPC classification number: G11C8/00 ,  G11C16/102 ,  G11C8/04

Abstract: An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

Abstract translation: 公开了一种具有附加电路的集成电路存储器，其中集成电路充当计数存储器。 存储器核心包括在相关联的电路中，允许以与普通随机存取存储器（RAM）相同的方式访问存储器核心。 计数器被包括并被耦合，使得它可以接收存储器核心中的任何位置的内容。 内存中的每个地址都充当个别计数器。 当呈现特定存储器地址指示该存储器位置处的计数应当递增时，该存储器位置的内容被传送到计数器，计数器递增，并且计数器的内容然后被传送回存储器位置 。 每当呈现指示要记录的新事件的新地址时，重复此过程。 在一系列事件结束时，核心内存将在每个对应的内存位置包含分配给该地址的事件的发生次数。

公开(公告)号：US20160071582A1

公开(公告)日：2016-03-10

申请号：US14940012

申请日：2015-11-12

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C13/00 ,  G11C11/16 ,  G11C17/16

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0069 ,  G11C17/146 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L29/785 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.

Abstract translation: 公开了一种可在低电压下读取的可编程电阻器件（PRD）存储器。 PRD包括至少一个可编程电阻元件（PRE），其中一端耦合到第一电源电压线，另一端耦合到至少一个选择器和至少一个读取选择器。 读取选择器分别包括耦合到第二和/或第三电源电压线的至少一个读取源极线（SLR）和/或一个读取使能（ENR）。 读选择器包括由核心逻辑器件构建的至少一个MOS器件。 至少一个PRD单元中的PRE可以被配置为通过向第一，第二和/或第三电压供应线施加电压来读取，从而将PRE电阻感测到逻辑状态。 可编程电阻元件可以在OTP，MTP，浮动栅极器件，反熔丝或新兴存储器（例如PCRAM，RRAM或MRAM等）中具有至少一个元件。

公开(公告)号：US20160019983A1

公开(公告)日：2016-01-21

申请号：US14545775

申请日：2015-06-16

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C29/00 ,  G11C17/18 ,  G11C17/08 ,  G11C17/16

CPC classification number: G11C29/78 ,  G11C17/16 ,  G11C17/18 ,  G11C29/702

Abstract: A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.

Abstract translation: 公开了一种在一次可编程（OTP）存储器中修复每个I / O不超过一个缺陷的新型冗余方案。 OTP存储器具有多个I / O中的多个OTP单元和与每个I / O相关联的至少一个辅助OTP单元。 每个I / O中的至少一个易失性单元对应于辅助OTP单元。 至少一个布尔门，用于根据易失性单元格中的数据独立地将数据反转到每个I / O中的主OTP存储器和/或从主OTP存储器中退出。 如果发现每个I / O不超过一个缺陷，则可以反转OTP存储器的每个I / O中的数据。 此外，可以通过读取辅助OTP单元并通过在初始化时自动生成至少一个读取周期来存储到易失性单元中来实现反演方案。

公开(公告)号：US09183897B2

公开(公告)日：2015-11-10

申请号：US14042392

申请日：2013-09-30

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C7/06 ,  G11C7/22 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C7/065 ,  G11C7/227 ,  G11C11/418 ,  G11C11/419

Abstract: Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.

Abstract translation: 公开了用于精确自定时SRAM存储器的电路和方法来跟踪字线和/或位线/位线条（BL / BLB）传播延迟。 可以将至少一个参考单元放置在驱动器的远端附近以驱动所选择的字线或参考字线。 当字线和/或参考字线被打开时，可以不早于任何选择的SRAM单元选择参考单元，并且可以激活不迟于激活BL或BLB的任何选择的SRAM单元的参考位线（RBL）。 RBL的激活可用于触发至少一个读出放大器。 在读出放大器操作完成以后，也可以使用RBL来取消选择字线或参考字线，以节省功耗。

公开(公告)号：US09076526B2

公开(公告)日：2015-07-07

申请号：US14021990

申请日：2013-09-09

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C15/00 ,  G11C15/04 ,  G11C17/08 ,  G11C17/16

CPC classification number: G11C15/04 ,  G11C17/08 ,  G11C17/16

Abstract: Techniques, systems and circuitry for using One-Time Programmable (OTP) memories to function as a Multiple-Time Programmable (MTP) memory. The OTP-for-MTP memory can include at least one OTP data memory to store data, and at least one OTP CAM to store addresses and to search input address through valid entries of the OTP CAM to find a latest entry of the matched valid addresses. The OTP-for-MTP memory can also include a valid-bit memory to find a next available entry of the OTP data memory and OTP CAM. When programming the OTP-for-MTP memory, address and data can be both programmed into the next available entry of the OTP CAM and the OTP data memory, respectively. When reading the OTP-for-MTP memory, the input address can be used to compare with valid entries of the addresses stored in the OTP CAM so that the latest entry of the matched valid addresses can be output.

Abstract translation: 使用一次性可编程（OTP）存储器作为多时间可编程（MTP）存储器的技术，系统和电路。 OTP-for-MTP存储器可以包括至少一个用于存储数据的OTP数据存储器，以及至少一个OTP CAM来存储地址，并且通过OTP CAM的有效条目搜索输入地址，以找到匹配的有效地址的最新条目 。 OTP-for-MTP存储器还可以包括有效位存储器，以找到OTP数据存储器和OTP CAM的下一个可用条目。 当对OTP-for-MTP存储器进行编程时，地址和数据可以分别编程到OTP CAM和OTP数据存储器的下一个可用条目中。 当读取OTP-for-MTP存储器时，可以使用输入地址与存储在OTP CAM中的地址的有效条目进行比较，以便可以输出匹配的有效地址的最新条目。

公开(公告)号：US09042153B2

公开(公告)日：2015-05-26

申请号：US13590049

申请日：2012-08-20

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  G11C17/16

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C17/16 ,  G11C2013/0042 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74

Abstract: A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure.

Abstract translation: 用于可编程电阻存储器以提高产量和可靠性的方法和系统具有多个可编程电阻单元。 每个可编程电阻单元可以具有至少一个可编程电阻单元。 每个可编程电阻单元可以具有可编程电阻元件，其第一端耦合到第一电源电压线，而第二端耦合到用作程序选择器的至少一个二极管。 每个二极管可以具有至少具有第一和第二类掺杂剂的第一和第二端子，其中第二端子耦合到第二电源电压线。 二极管的第一和第二端子可以由用于MOS器件的阱中的MOS的源极/漏极制造或者制造在相同的多晶硅结构上。

公开(公告)号：US09025357B2

公开(公告)日：2015-05-05

申请号：US13590047

申请日：2012-08-20

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  G11C17/16

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C17/16 ,  G11C19/08 ,  G11C2013/0042 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74

Abstract: A method and system of a programmable resistive memory having a plurality of programmable resistive memory units. At least one of the programmable resistive memory units has at least one data cell and at least one reference cell. The data cell can have one programmable resistive element coupled to at least one diode as a program selector and also coupled to a bitline (BL). The reference cell can have a reference resistive element coupled to at least one reference diode as reference program selector and also coupled to a reference bitline (BLR). In one embodiment, the reference resistive element can have substantially the same material, structure, or shape of the programmable resistive element. In one embodiment, the reference diode can have the same material, structure, or shape of the diode serving as the program selector diode.

Abstract translation: 一种具有多个可编程电阻存储器单元的可编程电阻存储器的方法和系统。 至少一个可编程电阻存储器单元具有至少一个数据单元和至少一个参考单元。 数据单元可以具有耦合到至少一个二极管作为程序选择器并且还耦合到位线（BL）的一个可编程电阻元件。 参考单元可以具有耦合到至少一个参考二极管作为参考程序选择器并且还耦合到参考位线（BLR）的参考电阻元件。 在一个实施例中，参考电阻元件可以具有与可编程电阻元件基本相同的材料，结构或形状。 在一个实施例中，参考二极管可以具有与编程选择二极管相同的二极管相同的材料，结构或形状。

公开(公告)号：US20150078060A1

公开(公告)日：2015-03-19

申请号：US14553874

申请日：2014-11-25

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C8/18 ,  G11C17/00

CPC classification number: G11C8/18 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C17/00 ,  G11C2216/30

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. The low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. In some applications where only the integrated circuit can read the data, a second control signal internal to the integrated circuit generates start, stop, device ID, read pattern, starting address, and actual read cycles, while the first control signal external to the integrated circuit can do the same for the program or erase path. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.

Abstract translation: 在集成电路中提供的低引脚数非易失性（NVM）存储器。 低引脚数非易失性（NVM）存储器只能使用一个外部控制信号和一个内部时钟信号来产生启动，停止，器件ID，读/写/擦除模式，起始地址和实际读/ 擦除周期。 当编程或擦除开始时，控制信号的切换递增/递减编程或擦除地址，并且控制信号的脉冲宽度决定实际的编程或擦除时间。 低引脚数非易失性（NVM）存储器中的数据可以与控制信号复用。 在只有集成电路可以读取数据的一些应用中，集成电路内部的第二控制信号产生启动，停止，器件ID，读取模式，起始地址和实际读取周期，而集成电路外部的第一个控制信号 电路可以做同样的程序或擦除路径。 由于可以从集成电路的系统时钟导出和共享时钟信号，所以NVM存储器只需要一个用于I / O事务的外部控制引脚来实现低引脚数接口。

公开(公告)号：US08817563B2

公开(公告)日：2014-08-26

申请号：US13214198

申请日：2011-08-21

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C7/02 ,  G11C13/00 ,  G11C17/16 ,  G11C11/16 ,  H01L29/78

CPC classification number: H01L27/2436 ,  G11C8/14 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

Abstract: A sensing circuit for programmable resistive device using diode as program selector is disclosed. The sensing circuit can have a reference and a sensing branch. In one embodiment, each branch can have a first type of MOS with the source coupled to a first supply voltage, the drain coupled to the drain of a second type of MOS, which can have the gate coupled to a bias supply voltage. The sources of the second type of MOS in the reference and sensing branches can be coupled to a reference resistor and a programmable resistance element, respectively, and they are further coupled to a second supply voltage through their diodes. The gate of the first type of MOS in the sensing branch can be coupled to the gate of the first type of MOS in the reference branch, which can have the drain coupled to the gate. The resistance difference between the reference resistor and the programmable resistive element can be sensed through the drain of the first type of MOS in the sensing branch into a logic level.

Abstract translation: 公开了一种使用二极管作为程序选择器的可编程电阻器件的感测电路。 感测电路可以具有参考和感测分支。 在一个实施例中，每个分支可以具有耦合到第一电源电压的源极的第一类型的MOS，漏极耦合到第二类型的MOS的漏极，其可以使栅极耦合到偏置电源电压。 参考和感测分支中的第二类型MOS的源极可分别耦合到参考电阻和可编程电阻元件，并且它们还通过其二极管耦合到第二电源电压。 感测支路中的第一类MOS的栅极可以耦合到参考支路中的第一类MOS的栅极，该基极可以将漏极耦合到栅极。 参考电阻和可编程电阻元件之间的电阻差可以通过感测分支中的第一类MOS的漏极检测到逻辑电平。

公开(公告)号：US20140211567A1

公开(公告)日：2014-07-31

申请号：US14231413

申请日：2014-03-31

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C7/10 ,  G11C16/10 ,  G11C29/02 ,  G11C17/00

CPC classification number: G11C17/18 ,  G11C7/10 ,  G11C8/18 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C17/00 ,  G11C17/146 ,  G11C17/16 ,  G11C29/022 ,  G11C29/027 ,  G11C29/1201 ,  G11C29/46 ,  G11C2216/30

Abstract: A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.

Abstract translation: 可以访问嵌入集成电路的低引脚数非易失性存储器（NVM），无需任何额外的引脚。 NVM具有一个或多个存储器单元，并且至少一个NVM单元可以具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。 选择器可以耦合到第二电源电压线并且具有选择信号。 集成电路可以包括至少一个测试模式检测电路，用于在检测到异常（或正常））操作条件时激活测试模式。 一旦测试模式被激活，集成电路的至少一个I / O或电源电压可以用作NVM的I / O或电源电压，以选择至少一个NVM单元进行读取，编程为非易失性或易失性 州。 在至少一个电源电压线的斜坡期间可以读取至少一个NVM单元。