公开(公告)号：US20110049624A1

公开(公告)日：2011-03-03

申请号：US12548005

申请日：2009-08-26

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78624

Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Abstract translation: 公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。 在半导体层中形成源延伸和漏扩展区。 在半导体层中形成深漏极区域和深源极区域。 第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触 并且栅极屏蔽金属沉积物抵靠深漏极区域。 在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

公开(公告)号：US09082856B2

公开(公告)日：2015-07-14

申请号：US13613198

申请日：2012-09-13

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract translation: 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US09064842B2

公开(公告)日：2015-06-23

申请号：US13425302

申请日：2012-03-20

Applicant: Ageeth Anke Bol ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Ageeth Anke Bol ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/417 ,  H01L21/02 ,  C01B31/04 ,  H01L29/16

CPC classification number: H01L29/41733 ,  C01B32/19 ,  H01L21/02527 ,  H01L29/1606 ,  H01L29/778 ,  Y10S977/734

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract translation: 半导体器件包括衬底，形成在衬底中的第一多个触点，形成在衬底上的石墨烯层和在第一多个触点上形成的第二多个触点和形成在石墨烯层上的第二多个触点，使得石墨烯层形成在第一多个触点和 第二个复数接触。

公开(公告)号：US09045842B2

公开(公告)日：2015-06-02

申请号：US13617727

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00 ,  C25F5/00 ,  B32B38/10 ,  C25F3/02 ,  C01B31/04

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括输出电流的电力，以及容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US08946853B2

公开(公告)日：2015-02-03

申请号：US13351041

申请日：2012-01-16

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

Abstract translation: 在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁 区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

公开(公告)号：US08772782B2

公开(公告)日：2014-07-08

申请号：US13303785

申请日：2011-11-23

Applicant: Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

Inventor： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/12

CPC classification number: H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

公开(公告)号：US08536651B2

公开(公告)日：2013-09-17

申请号：US13604340

申请日：2012-09-05

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Abstract translation: 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

公开(公告)号：US20130234762A1

公开(公告)日：2013-09-12

申请号：US13418066

申请日：2012-03-12

Applicant: Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

Inventor： Shu-Jen Han ,  Yu-Ming Lin ,  Yanqing Wu

IPC: H03K3/00 ,  H01L29/775

CPC classification number: H01L29/42364 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66431 ,  H01L29/7781 ,  H01L29/78684

Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Abstract translation: 电路包括包括栅极和石墨烯通道的负差分电阻（NDR）器件和调制栅极上的栅极电压的栅极电压源，使得通过石墨烯通道的电流呈现负的差分电阻。

公开(公告)号：US20130175633A1

公开(公告)日：2013-07-11

申请号：US13607589

申请日：2012-09-07

Applicant: Martin M. Frank ,  Dechao Guo ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Martin M. Frank ,  Dechao Guo ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L27/092

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/413 ,  H01L51/0558

Abstract: A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.

Abstract translation: 场效应晶体管制造方法包括：在衬底上限定栅极结构，在栅极结构上沉积介电层，在介电层上沉积第一金属层，去除第一金属层的一部分，沉积第二金属层，退火 第一和第二金属层，并且在电介质层和栅极结构上限定碳基器件。

公开(公告)号：US08471249B2

公开(公告)日：2013-06-25

申请号：US13104591

申请日：2011-05-10

Applicant: Hsin-Ying Chiu ,  Shu-Jen Han ,  Hareem T. Maune

Inventor： Hsin-Ying Chiu ,  Shu-Jen Han ,  Hareem T. Maune

IPC: H01L29/08

CPC classification number: H01L29/7781 ,  B82Y10/00 ,  H01L29/42364 ,  H01L29/66462 ,  H01L51/0048 ,  H01L51/0529 ,  H01L51/0558

Abstract: Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance. For example, a carbon field effect transistor includes a channel comprising a carbon nanostructure formed on an insulating layer, a gate structure formed on the channel, a monolayer of DNA conformally covering the gate structure and a portion of the channel adjacent the gate structure, an insulating spacer conformally formed on the monolayer of DNA, and source and drain contacts connected by the channel.

Abstract translation: 具有由诸如碳纳米管或石墨烯之类的碳纳米结构形成的通道的碳晶体管器件以及具有带电单层以降低通道的未门控区域中的寄生电阻的方法以及用于制造具有带电单层以降低寄生电阻的碳晶体管器件的方法。 例如，碳场效应晶体管包括通道，其包括在绝缘层上形成的碳纳米结构，在沟道上形成的栅极结构，保形地覆盖栅极结构的DNA单层和邻近栅极结构的沟道的一部分， 在DNA的单层上保形地形成绝缘垫片，以及由通道连接的源极和漏极触点。