公开(公告)号：US20050206394A1

公开(公告)日：2005-09-22

申请号：US10806680

申请日：2004-03-22

申请人： Narain Arora ,  Li Song ,  Aki Fujimura

发明人： Narain Arora ,  Li Song ,  Aki Fujimura

IPC分类号： H01L21/66 ,  G01R27/26 ,  G01R31/08 ,  G01R31/28 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/544 ,  H01L27/04

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  G06F17/5018 ,  G06F2217/78 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.

摘要翻译： 本发明涉及用于测量集成电路互连工艺参数的技术。 这些技术适用于由任何类型的导电材料制成的任何非理想形状的互连。 测试结构在集成电路内制造。 从测试结构获取非破坏性电测量，以确定与测试结构相关联的耦合电容。 场求解器使用初始过程参数来确定设计耦合电容。 然后，优化器使用测量的耦合电容和设计耦合电容来确定互连工艺参数。

公开(公告)号：US06948141B1

公开(公告)日：2005-09-20

申请号：US10281427

申请日：2002-10-24

申请人： Akella V. S. Satya ,  Vladimir D. Federov ,  Li Song

发明人： Akella V. S. Satya ,  Vladimir D. Federov ,  Li Song

IPC分类号： G01R31/3183 ,  G06F17/50

CPC分类号： G01R31/318364 ,  G06F17/5068 ,  H01J2237/2817

摘要： Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

摘要翻译： 公开了高效准确地计算关键区域的机制。 一般来说，公开了一种确定半导体设计布局的关键区域的方法。 关键区域可用于预测由这种布局制造的半导体器件的产量。 首先提供具有多个特征的半导体设计布局。 特征具有包括非矩形多边形形状的多个多边形形状。 每个特征形状至少有一个属性或工件，例如顶点或边。 基于至少两个特征形状属性或伪影之间的距离来计算失败函数的概率。 作为示例实现，首先确定两个相邻特征边缘（或顶点）之间的距离或相同特征的两个特征边缘（或顶点）之间的距离，然后用于计算故障功能的概率。 在特定方面，首先用距离来确定相同特征形状中的相邻特征或中线之间的中线，然后使用中线来确定失败功能的概率。 然后根据所确定的故障功能概率来确定设计布局的关键区域。 在具体实施中，缺陷类型是短型缺陷或开放型缺陷。 在优选的实施方案中，特征可以具有任何合适的多边形形状，如在设计布局中典型的。

公开(公告)号：US06918101B1

公开(公告)日：2005-07-12

申请号：US10281416

申请日：2002-10-24

申请人： Akella V. Satya ,  Raman K. Nurani ,  Li Song

发明人： Akella V. Satya ,  Raman K. Nurani ,  Li Song

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

摘要翻译： 公开了高效准确地计算关键区域的机制。 一般来说，公开了一种用于确定半导体设计布局的临界区域的方法。 关键区域可用于预测由这种布局制造的半导体器件的产量。 首先提供具有多个特征的半导体设计布局。 特征具有包括非矩形多边形形状的多个多边形形状。 每个特征形状至少有一个属性或工件，例如顶点或边。 基于至少两个特征形状属性或伪影之间的距离来计算失败函数的概率。 作为示例实现，首先确定两个相邻特征边缘（或顶点）之间的距离或相同特征的两个特征边缘（或顶点）之间的距离，然后用于计算故障功能的概率。 在特定方面，首先用距离来确定相同特征形状中的相邻特征或中线之间的中线，然后使用中线来确定失败功能的概率。 然后根据所确定的故障功能概率来确定设计布局的关键区域。 在具体实施中，缺陷类型是短型缺陷或开放型缺陷。 在优选的实施方案中，特征可以具有任何合适的多边形形状，如在设计布局中典型的。

公开(公告)号：US06813572B2

公开(公告)日：2004-11-02

申请号：US10281432

申请日：2002-10-24

申请人： Akella V.S. Satya ,  Li Song ,  Robert Thomas Long ,  Kurt H. Weiner

发明人： Akella V.S. Satya ,  Li Song ,  Robert Thomas Long ,  Kurt H. Weiner

IPC分类号： G06F1900

CPC分类号： G01R31/287 ,  G01R31/2831 ,  G01R31/2856 ,  G01R31/2858 ,  G01R31/2894

摘要： Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

摘要翻译： 公开了用于确定是否对诸如产品晶片或产品晶片批次的半导体产品进行老化的方法和装置。 通常，检查半导体产品上的测试结构以提取诸如缺陷密度的产量信息。 由于该产量信息与早期或非本征瞬时故障率相关，因此可以基于该产量信息来确定一个或多个故障机制的瞬时外在故障率，例如电迁移，栅极氧化物分解或热载流子注入。 然后，根据所确定的瞬时故障率，确定是否对半导体产品进行老化。