公开(公告)号：US20130258532A1

公开(公告)日：2013-10-03

申请号：US13431347

申请日：2012-03-27

申请人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

发明人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H01L27/06 ,  H01L21/20 ,  H01L21/33 ,  G06F17/50 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/73 ,  H02H7/20 ,  H01L21/331

CPC分类号： H01L27/0262 ,  G06F17/5072 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0255 ,  H01L27/06 ,  H01L27/1211 ,  H01L29/06

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

公开(公告)号：US20130009207A1

公开(公告)日：2013-01-10

申请号：US13614072

申请日：2012-09-13

申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC分类号： H01L29/74

CPC分类号： H01L29/74 ,  H01L21/823892 ,  H01L27/0262 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

摘要翻译： 使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。 垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。 也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

公开(公告)号：US20110185332A1

公开(公告)日：2011-07-28

申请号：US12695494

申请日：2010-01-28

申请人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

发明人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US20100230732A1

公开(公告)日：2010-09-16

申请号：US12547529

申请日：2009-08-26

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  WiIliam R. Tonti ,  Yun Shi

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  WiIliam R. Tonti ,  Yun Shi

IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L21/30

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

摘要翻译： 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US20100096536A1

公开(公告)日：2010-04-22

申请号：US12646292

申请日：2009-12-23

申请人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： G01J1/44

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。 不需要额外的引脚。

公开(公告)号：US20090310267A1

公开(公告)日：2009-12-17

申请号：US12140485

申请日：2008-06-17

申请人： Robert J. Gauthier, JR. ,  Junjun Li ,  Ankit Srivastava

发明人： Robert J. Gauthier, JR. ,  Junjun Li ,  Ankit Srivastava

IPC分类号： H02H9/00

CPC分类号： H03F3/45188 ,  H01L27/0251 ,  H03F1/52 ,  H03F1/523 ,  H03F2203/45466 ,  H03F2203/45486 ,  H03F2203/45504

摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.

摘要翻译： 在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

公开(公告)号：US20090267178A1

公开(公告)日：2009-10-29

申请号：US12108924

申请日：2008-04-24

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

IPC分类号： H01L29/06

CPC分类号： H01L29/7436 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

摘要： Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

摘要翻译： 用于在绝缘体上半导体（SOI）衬底中制造的有源器件的器件结构和用于射频集成电路的设计结构。 器件结构包括半导体层中从半导体层的顶表面延伸到第一深度的第一隔离区域，半导体层中的从半导体层的顶表面延伸到第二深度更大的第二隔离区域 比第一深度，以及半导体层中的第一掺杂区域。 第一掺杂区域垂直地设置在第一隔离区域和设置在SOI衬底的半导体层和处理晶片之间的绝缘层之间。 装置结构可以包括在体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构中。

公开(公告)号：US20090179267A1

公开(公告)日：2009-07-16

申请号：US12013101

申请日：2008-01-11

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

IPC分类号： H01L27/12 ,  H01L21/786

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

摘要翻译： 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

公开(公告)号：US20090140338A1

公开(公告)日：2009-06-04

申请号：US11949973

申请日：2007-12-04

申请人： Robert J. Gauthier, JR. ,  Rajendran Krishnasamy

发明人： Robert J. Gauthier, JR. ,  Rajendran Krishnasamy

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.

摘要翻译： 一种用于制造氧化硅（SOI）衬底上的集成电路的FET晶体管的方法和结果，包括以下步骤：在衬底上的栅极两侧的衬底中形成凹槽，将氧离子注入到凹槽中，并退火 将氧离子转换成每个凹槽下方的SOI层的衬底。

公开(公告)号：US20090089719A1

公开(公告)日：2009-04-02

申请号：US12127245

申请日：2008-05-27

申请人： Robert J. Gauthier, JR. ,  Junjun Li

发明人： Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H02H9/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

摘要翻译： 用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。