公开(公告)号：US5525890A

公开(公告)日：1996-06-11

申请号：US101768

申请日：1993-08-04

申请人： Satoshi Iwatsu ,  Kazunori Ozawa ,  Masana Ugaji ,  Yoshio Nishi ,  Yasuhito Eguchi

发明人： Satoshi Iwatsu ,  Kazunori Ozawa ,  Masana Ugaji ,  Yoshio Nishi ,  Yasuhito Eguchi

IPC分类号： G01R31/36 ,  H01M10/48 ,  H01M10/44

CPC分类号： G01R31/3648 ,  G01R31/3658 ,  Y10S320/21

摘要： A battery unit of a cartridge type for use as a power supply for electric motorcars, broadcasting apparatus and the like comprises a battery, a monitoring unit for monitoring the condition of the battery and storing information about the battery, a display for displaying data obtained by the monitoring unit, an I/O unit for sending out data representing the condition of the battery monitored by the monitoring unit to an external device, and a battery identification output unit for sending out a battery identification signal representing the type of the battery. The monitoring unit comprises a voltage measuring unit for measuring the supply voltage of the battery, a current measuring unit for measuring the current supplied from the battery, a temperature sensor for sensing the temperature of the battery, and a clock for indicating passage of time. The monitoring unit determines the quantity of residual electrical energy remaining in the battery when replacing the battery with a fully charged battery.

摘要翻译： 作为用于电动马达，广播装置等的电源的盒式电池单元包括电池，用于监视电池的状况并存储关于电池的信息的监视单元，用于显示由 监视单元，用于将表示由监视单元监视的电池的状态的数据发送到外部设备的I / O单元，以及用于发送表示电池类型的电池识别信号的电池识别输出单元。 监视单元包括用于测量电池的电源电压的电压测量单元，用于测量从电池供应的电流的电流测量单元，用于感测电池的温度的温度传感器和用于指示时间流逝的时钟。 当用完全充电的电池更换电池时，监控单元确定电池中剩余电能的数量。

公开(公告)号：US5330036A

公开(公告)日：1994-07-19

申请号：US154388

申请日：1993-11-18

申请人： Yoshio Nishi ,  Haruo Kubota ,  Yoshio Ueno ,  Munenobu Honda

发明人： Yoshio Nishi ,  Haruo Kubota ,  Yoshio Ueno ,  Munenobu Honda

IPC分类号： B66D3/14 ,  B66D5/14 ,  B66D5/22 ,  F16D65/12 ,  F16D69/00 ,  F16D69/02 ,  F16D13/64 ,  F16D65/02

CPC分类号： B66D5/22 ,  B66D3/14 ,  F16D65/127 ,  F16D69/02

摘要： A mechanical brake for a hoist and traction machine, which is provided with brake releasing force control layers at braking surfaces of a driving member opposite to lining plates. Each of the brake releasing force control layers comprising a heat-treated plating layer made of nickel phosphate, nickel chromium or chromium, so that the surface condition of each braking surface of the driving member can be controlled and the surface hardness can be controlled, whereby an initial force for the brake releasing during the lowering of a load or the releasing traction of a load is adapted to be lower.

摘要翻译： 一种用于起重和牵引机械的机械制动器，其在与衬板相对的驱动构件的制动表面处设置有制动释放力控制层。 每个制动解除力控制层包括由镍磷酸盐，镍铬或铬制成的热处理镀层，使得可以控制驱动构件的每个制动表面的表面状态并且可以控制表面硬度，由此 用于在降低负载期间制动器释放的初始力或负载的释放牵引力的初始力适合于较低。

公开(公告)号：US4523213A

公开(公告)日：1985-06-11

申请号：US396843

申请日：1982-07-09

申请人： Masami Konaka ,  Hiroshi Iwai ,  Yoshio Nishi

发明人： Masami Konaka ,  Hiroshi Iwai ,  Yoshio Nishi

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66772 ,  H01L21/26533 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/78654 ,  Y10S148/082

摘要： An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.

摘要翻译： 一种MOS半导体器件，其中氧化硅或氮化硅的掩埋区域部分地延伸到MOS晶体管的沟道区的底部平面上。

公开(公告)号：US4153487A

公开(公告)日：1979-05-08

申请号：US822194

申请日：1977-08-05

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/8226 ,  H01L21/033 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US4151019A

公开(公告)日：1979-04-24

申请号：US822322

申请日：1977-08-05

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/02 ,  H01L21/22 ,  H01L21/76 ,  H01L27/04

CPC分类号： H01L21/033 ,  H01L21/8226 ,  H01L27/0233

摘要： A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

摘要翻译： 通过蒸气外延生长技术在N型半导体层上形成P型半导体层，在P型半导体层上形成绝缘膜，通过绝缘膜设置栅格状的第一开口。 然后，磷通过栅格形状开口扩散到P型半导体层中，以形成延伸穿过半导体层的第一N型区域到达N型半导体层。 然后，通过由栅格形状的第一开口分隔并被其包围的绝缘膜的各个部分形成第二开口，并且硼通过第一和第二开口扩散，以形成网格形状的第一N型区域中的第一和第二P型区域， P型半导体层。 最后，通过绝缘膜的各部分形成第三开口，并且磷通过第三开口扩散到P型半导体层中，以形成第二N型区域，从而形成包括横向PNP晶体管和垂直NPN的集成注入逻辑半导体器件 晶体管。

公开(公告)号：US4119998A

公开(公告)日：1978-10-10

申请号：US815768

申请日：1977-07-14

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/02 ,  H01L27/04

CPC分类号： H01L27/0233

摘要： An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.

摘要翻译： 集成注入逻辑半导体器件由N型半导体衬底，P型层，形成为穿透P型半导体层并接触N型半导体衬底的第一N型区域构成，形成第二N型区域 在P型半导体层中形成的P型区域和形成在第一N型区域中的P型区域。 围绕所述第一和第二N型区域并穿过P型半导体层设置第三N型区域。 I2L电路由发射极，基极和集电极分别由所述P型区域，所述第一N型区域和所述P型半导体层分别构成的横向PNP晶体管和其发射极，基极和集电极构成的垂直NPN晶体管构成 分别由所述N型半导体衬底，所述P型半导体层和所述第二N型区域。

公开(公告)号：US4106045A

公开(公告)日：1978-08-08

申请号：US686537

申请日：1976-05-14

申请人： Yoshio Nishi

发明人： Yoshio Nishi

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/74 ,  H01L27/12 ,  H01L29/73 ,  H01L29/786

CPC分类号： H01L29/78612 ,  H01L21/743 ,  H01L29/78609 ,  H01L29/78657

摘要： A field effect transistor includes a thin silicon layer formed on a sapphire substrate and having source, gate and drain regions. A buried layer of the same conductivity type as that of the gate region and a higher impurity concentration than that of the gate region at the lower portion of a junction between the source and gate regions.

摘要翻译： 场效应晶体管包括形成在蓝宝石衬底上并具有源极，栅极和漏极区域的薄硅层。 与栅极区域相同的导电类型的掩埋层和比源极和栅极区域之间的结的下部的栅极区域的杂质浓度更高的杂质浓度。

公开(公告)号：US4064526A

公开(公告)日：1977-12-20

申请号：US644048

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L29/73 ,  H01L27/04 ,  H01L29/36 ,  H01L29/72

CPC分类号： H01L27/0237 ,  Y10S148/085 ,  Y10S148/087 ,  Y10S148/167

摘要： An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate. An integrated injection logic circuit is comprised of a lateral NPN transistor whose emitter, base and collector are constituted by said first P type region, first N type region and P type semiconductor layer, respectively, and a vertical PNP transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, P type semiconductor layer plus second P type region, and second N type region, respectively.

摘要翻译： 一种集成注入逻辑半导体器件，包括N型半导体衬底，层叠在所述半导体衬底上的P型半导体层和以穿过所述P型半导体层的方式形成以到达所述N型半导体衬底的N型第一区域，第一 形成在所述第一N型区域中的P型区域，形成在所述P型半导体层中的第二N型区域和形成在所述第二N型区域和所述N型半导体衬底之间的第二P型区域， 型半导体衬底。 集成注入逻辑电路由横向NPN晶体管组成，其发射极，基极和集电极分别由所述第一P型区域，第一N型区域和P型半导体层构成，垂直PNP晶体管的发射极，基极和集电极 分别由所述N型半导体衬底，P型半导体层加上第二P型区域和第二N型区域构成。

公开(公告)号：US4054900A

公开(公告)日：1977-10-18

申请号：US644293

申请日：1975-12-24

申请人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

发明人： Yukuya Tokumaru ,  Masanori Nakai ,  Satoshi Shinozaki ,  Junichi Nakamura ,  Shintaro Ito ,  Yoshio Nishi

IPC分类号： H01L27/02 ,  H01L29/72 ,  H01L27/04 ,  H03K19/08

CPC分类号： H01L27/0233

摘要： An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.

摘要翻译： 一种包括N型半导体衬底的集成注入逻辑半导体器件; 叠置在N型半导体衬底上的P型半导体层; 形成在P型半导体层中的第一N型区域; 形成在P型半导体层中的第二N型区域; 以及形成在所述第一N型区域中的P型区域，其中所述第一N型区域通过形成在所述第一N型区域和N型半导体衬底之间的N型连接器区域与所述N型半导体衬底连接。

公开(公告)号：US09184099B2

公开(公告)日：2015-11-10

申请号：US13252315

申请日：2011-10-04

申请人： Kosar Baghbani-Parizi ,  Yoshio Nishi ,  Hesaam Esfandyarpour

发明人： Kosar Baghbani-Parizi ,  Yoshio Nishi ,  Hesaam Esfandyarpour

IPC分类号： G01N27/414 ,  H01L21/02 ,  H01L29/66 ,  H01L21/84 ,  B82Y15/00 ,  H01L27/12 ,  B01L3/00

CPC分类号： G01N27/4145 ,  B01L3/502715 ,  B01L3/502753 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/12 ,  B82Y15/00 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/84 ,  H01L27/1203

摘要： A sensing apparatus for sensing target materials including biological or chemical molecules in a fluid. One such apparatus includes a semiconductor-on-insulator (SOI) structure having an electrically-insulating layer, a fluidic channel supported by the SOI structure and configured and arranged to receive and pass a fluid including the target materials, and a semiconductor device including at least three electrically-contiguous semiconductor regions doped to exhibit a common polarity. The semiconductor regions include a sandwiched region sandwiched between two of the other semiconductor regions, and configured and arranged adjacent to the fluidic channel with a surface directed toward the fluidic channel for coupling to the target materials in the fluidic channel, and further arranged for responding to a bias voltage. The sensing apparatus also includes an amplification circuit in or on the SOI and that is arranged to facilitate sensing of the target material near the fluidic channel.

摘要翻译： 一种感测装置，用于感测流体中包括生物或化学分子的目标材料。 一种这样的设备包括具有电绝缘层的绝缘体上半导体（SOI）结构，由SOI结构支撑的流体通道，并且被构造和布置成接收和通过包括目标材料的流体，以及包括在 至少三个电连续的半导体区被掺杂以表现出共同的极性。 半导体区域包括夹在两个其它半导体区域之间的夹层区域，并且被配置和布置成与流体通道相邻，其表面指向流体通道，用于耦合到流体通道中的目标材料，并且还被布置为响应于 偏置电压。 感测装置还包括在SOI中或SOI上的放大电路，并且被布置成便于感测流体通道附近的目标材料。