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    Three-dimensional integrated circuits and techniques for fabrication thereof
    21.
    发明授权
    Three-dimensional integrated circuits and techniques for fabrication thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US07897428B2

    公开(公告)日：2011-03-01

    申请号：US12131988

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L27/12

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二键合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION
    22.
    发明申请
    CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION 有权
    CMOS兼容集成电介质光波导耦合器和制造

    公开(公告)号：US20090324162A1

    公开(公告)日：2009-12-31

    申请号：US12164580

    申请日：2008-06-30

    申请人： Solomon Assefa ,  Christopher Jahnes ,  Yurii Vlasov

    发明人： Solomon Assefa ,  Christopher Jahnes ,  Yurii Vlasov

    IPC分类号： G02B6/12 ,  H01L21/302

    CPC分类号： G02B6/30 ,  B82Y20/00 ,  G02B6/1223

    摘要： An optoelectronic circuit fabrication method and integrated circuit apparatus fabricated therewith. Integrated circuits are fabricated with an integral optical coupling transition to efficiently couple optical energy from an optical fiber to an integrated optical waveguide on the integrated circuit. Layers of specific materials are deposited onto a semiconductor circuit to support etching of a trench to receive an optical coupler that performs proper impedance matching between an optical fiber and an on-circuit optical waveguide that extends part way into the transition channel. A silicon based dielectric that includes at least a portion with a refractive index substantially equal to a section of the optical fiber is deposited into the etched trench to create the optical coupler. Silicon based dielectrics with graded indices are also able to be used. Chemical mechanical polishing is used finalize preparation of the optical transition and integrated circuit.

    摘要翻译： 一种光电子电路制造方法及其制造的集成电路装置。 集成电路采用集成光耦合过渡制造，以有效地将光能从光纤耦合到集成电路上的集成光波导。 特定材料的层被沉积到半导体电路上以支持蚀刻沟槽以接收光纤耦合器，该光耦合器在光纤和部分地延伸到过渡通道中的在线光波导之间执行适当的阻抗匹配。 包括折射率基本上等于光纤的一部分的至少一部分的硅基电介质被沉积到蚀刻沟槽中以产生光耦合器。 也可以使用具有分级指数的硅基电介质。 化学机械抛光用于确定光学转换和集成电路的准备。

    Techniques for Three-Dimensional Circuit Integration
    23.
    发明申请
    Techniques for Three-Dimensional Circuit Integration 有权
    三维电路集成技术

    公开(公告)号：US20090297091A1

    公开(公告)日：2009-12-03

    申请号：US12132029

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： G02B6/12 ,  H01L21/84 ,  H01L27/12

    CPC分类号： H01L27/0688

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，一种三维集成电路包括底部器件层和顶部器件层。 底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。 顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof
    24.
    发明申请
    Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof 有权
    三维集成电路及其制造技术

    公开(公告)号：US20090294814A1

    公开(公告)日：2009-12-03

    申请号：US12131988

    申请日：2008-06-03

    申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

    IPC分类号： H01L31/00 ,  H01L21/00

    CPC分类号： H01L27/0688 ,  H01L25/167 ,  H01L27/144 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

    摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

    摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。 顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
    26.
    发明申请
    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
    利用侧壁间隔物特征在集成电路中形成磁隧道结

    公开(公告)号：US20070166840A1

    公开(公告)日：2007-07-19

    申请号：US11333997

    申请日：2006-01-18

    申请人： Solomon Assefa ,  Michael Gaidis ,  Sivananda Kanakasabapathy ,  John Hummel ,  David Abraham

    发明人： Solomon Assefa ,  Michael Gaidis ,  Sivananda Kanakasabapathy ,  John Hummel ,  David Abraham

    IPC分类号： H01L21/00 ,  H01L29/94

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

    摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

    Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration
    30.
    发明授权
    Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration 失效
    在硅硅衬底上制造具有平面氧化物/ SOI界面的局部厚盒，用于硅光子学集成

    公开(公告)号：US08772902B2

    公开(公告)日：2014-07-08

    申请号：US13451141

    申请日：2012-04-19

    申请人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

    发明人： Solomon Assefa ,  William M. J. Green ,  Marwan H. Khater ,  Yurii A. Vlasov

    IPC分类号： H01L21/70

    CPC分类号： G02B6/13 ,  H01L21/76232 ,  H01L21/76289

    摘要： Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate.

    摘要翻译： 线槽形成在体半导体衬底和不透氧层的堆叠中，使得体半导体衬底中的沟槽的深度大于一对相邻定位的线沟槽之间的横向间隔。 不透水间隔物形成在线沟槽的侧壁上。 单独或与氧化组合的各向同性蚀刻从氧不透性间隔物的下面去除半导体材料，以扩大线沟槽的扩展底部的横向范围，并且减小相邻扩展底部之间的横向间隔 。 底部周围的半导体材料被氧化以形成在多个不透氧隔离物下面的半导体氧化物部分。 半导体绝缘体（SOI）部分形成在半导体氧化物部分之上和体半导体衬底内。