公开(公告)号：US07763508B2

公开(公告)日：2010-07-27

申请号：US12330292

申请日：2008-12-08

Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

公开(公告)号：US08664066B2

公开(公告)日：2014-03-04

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

公开(公告)号：US08390042B2

公开(公告)日：2013-03-05

申请号：US13353013

申请日：2012-01-18

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L29/43 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20120208337A1

公开(公告)日：2012-08-16

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US08119464B2

公开(公告)日：2012-02-21

申请号：US12561638

申请日：2009-09-17

Applicant: Rohit Pal ,  Stephan Waidmann

Inventor： Rohit Pal ,  Stephan Waidmann

IPC: H01L21/84

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110062519A1

公开(公告)日：2011-03-17

申请号：US12561638

申请日：2009-09-17

Applicant: Rohit Pal ,  Stephan Waidmann

Inventor： Rohit Pal ,  Stephan Waidmann

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

公开(公告)号：US07893496B2

公开(公告)日：2011-02-22

申请号：US12644882

申请日：2009-12-22

Applicant: Igor Peidous ,  Rohit Pal

Inventor： Igor Peidous ,  Rohit Pal

IPC: H01L27/12

CPC classification number: H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

Abstract: Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer

Abstract translation: 提供了应力增强型MOS晶体管。 提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。 绝缘体上半导体结构包括：衬底，半导体层和布置在衬底和半导体层之间的绝缘层。 半导体层具有第一表面，第二表面和第一区域。 栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

公开(公告)号：US07838308B2

公开(公告)日：2010-11-23

申请号：US12119196

申请日：2008-05-12

Applicant: Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

Inventor： Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66636 ,  H01L29/78

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract translation: 一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。 在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。 该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。 该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异 接近值。