公开(公告)号：US08084828B2

公开(公告)日：2011-12-27

申请号：US12815129

申请日：2010-06-14

Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

公开(公告)号：US07763508B2

公开(公告)日：2010-07-27

申请号：US12330292

申请日：2008-12-08

Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

公开(公告)号：US08390042B2

公开(公告)日：2013-03-05

申请号：US13353013

申请日：2012-01-18

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L29/43 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20100244156A1

公开(公告)日：2010-09-30

申请号：US12815129

申请日：2010-06-14

Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

公开(公告)号：US20120119308A1

公开(公告)日：2012-05-17

申请号：US13353013

申请日：2012-01-18

Applicant: Man Fai NG ,  Rohit Pal

Inventor： Man Fai NG ,  Rohit Pal

IPC: H01L29/772

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 包括金属栅电极的改进的半导体器件通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度而形成，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US08124515B2

公开(公告)日：2012-02-28

申请号：US12469418

申请日：2009-05-20

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3215

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度，形成包括金属栅电极的改进的半导体器件，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US20100295103A1

公开(公告)日：2010-11-25

申请号：US12469418

申请日：2009-05-20

Applicant: Man Fai Ng ,  Rohit Pal

Inventor： Man Fai Ng ,  Rohit Pal

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/32155 ,  H01L21/322 ,  H01L29/7833

Abstract: Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract translation: 通过降低覆盖在金属层上的硅层顶部的初始高掺杂剂浓度，形成包括金属栅电极的改进的半导体器件，具有降低的性能可变性。 实施例包括通过将反掺杂剂注入硅层的上部来去除高掺杂剂浓度部分并用未掺杂的或轻掺杂的硅代替它来减少硅层上部的掺杂剂浓度，并施加吸气 剂到硅层的上表面以形成具有吸收的掺杂剂的薄层，该层可以被去除或保留。

公开(公告)号：US08664057B2

公开(公告)日：2014-03-04

申请号：US13565970

申请日：2012-08-03

Applicant: Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

Inventor： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/28 ,  H01L21/44 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

Abstract translation: 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

公开(公告)号：US08373228B2

公开(公告)日：2013-02-12

申请号：US12687607

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20130032893A1

公开(公告)日：2013-02-07

申请号：US13550693

申请日：2012-07-17

Applicant: Rohit Pal ,  George Mulfinger

Inventor： Rohit Pal ,  George Mulfinger

IPC: H01L27/088 ,  H01L21/283

CPC classification number: H01L23/5256 ,  H01L23/485 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.

Abstract translation: 可以实现复杂半导体器件中的栅极高度缩放，而不需要重新设计非晶体管器件。 为此，可以将半导体电极材料的厚度适用于有源区域和接收非晶体管器件的隔离区域。 此后，可以执行适合的栅极层堆叠的实际图案化，以获得所需高度的栅电极结构，以改善特别是AC性能，而不需要重新设计非晶体管器件。