公开(公告)号：US20060242447A1

公开(公告)日：2006-10-26

申请号：US11088445

申请日：2005-03-23

Applicant: Sivakumar Radhakrishnan ,  Michael Wiznerowicz ,  Jed Griffin ,  Kapilan Maheswaran ,  Scott Rushford ,  David Hotz

Inventor： Sivakumar Radhakrishnan ,  Michael Wiznerowicz ,  Jed Griffin ,  Kapilan Maheswaran ,  Scott Rushford ,  David Hotz

IPC: G06F1/00

CPC classification number: G06F1/206 ,  G06F13/1668

Abstract: Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on the semiconductor device, comparing the detected temperature to a threshold, and generating a high interrupt if the temperature is above the threshold and a low interrupt if the temperature is below the threshold.

Abstract translation: 描述了数据处理环境中控制器的热控制。 在一个实施例中，本发明包括检测半导体器件上的热传感器上的半导体器件的温度，将检测到的温度与阈值进行比较，以及如果温度高于阈值则产生高中断，如果温度高于阈值则产生低中断 低于阈值。

公开(公告)号：US20060136611A1

公开(公告)日：2006-06-22

申请号：US10750060

申请日：2003-12-30

Applicant: William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

Inventor： William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

IPC: G06F13/28

CPC classification number: G06F13/4027

Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

Abstract translation: 用于第一设备的第二设备查询第二设备内的硬件特征的可用性的装置和方法，以及第二设备接收和分析查询以确定是否响应，取决于所寻求的硬件特征的版本 ，识别供应商等的代码，并且如果确定作出回复，则响应提供硬件特征的可用性的指示和/或可以访问硬件特征的地址。

公开(公告)号：US06049526A

公开(公告)日：2000-04-11

申请号：US916342

申请日：1997-08-22

Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Wong

Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Wong

IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/22

CPC classification number: H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04L2012/568

Abstract: An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network in which each cell is characterized by a virtual circuit communication channel and in which each virtual circuit is characterized by one or more profiles. Each profile has a group of sub-profiles, with each sub-profile having a unique bandwidth allocation component. The scheduler incorporates a profile queue buffer for receiving, pairing and storing the profiles and sub-profiles and, a link list processor coupled to the profile queue buffer to receive the profile, sub-profile pairs. The link list processor detects null profile, sub-profile pairs in the buffer and, over-write them with a selected one of the virtual circuit profile, sub-profile pairs. A valid pending register of length p bits, and a memory are coupled to the link list processor. The memory stores pointers to link lists of virtual circuits associated with each of the profile, sub-profile pairs received by the link list processor. The pointers comprise, for each of the link lists, a head pointer to a first entry in the link list and a next pointer to a virtual circuit in the link list last associated by the link list processor with one of the profile, sub-profile pairs.

Abstract translation: 一种用于在通信网络中的多个小区的异步传输模式通信的可用比特率调度器，其中每个小区的特征在于虚拟电路通信信道，并且其中每个虚拟电路由一个或多个简档表征。 每个配置文件具有一组子配置文件，每个子配置文件具有唯一的带宽分配组件。 调度器包括用于接收，配对和存储简档和子简档的简档队列缓冲器，以及耦合到简档队列缓冲器以接收简档的子配置对的链接列表处理器。 链路列表处理器检测缓冲器中的零配置文件，子配置对，并用虚拟电路配置文件，子配置对中的所选择的一个来对其进行写写。 长度为p比特的有效等待寄存器和存储器耦合到链路列表处理器。 存储器存储指向与链接列表处理器接收的每个简档，子简档对相关联的虚拟电路的链接列表的指针。 所述指针针对每个所述链接列表包括到所述链接列表中的第一条目的头指针，以及指向所述链接列表中最后一个与所述链接列表处理器相关联的虚拟电路的下一个指针，其中所述简档，子简档 对。

公开(公告)号：US20140189212A1

公开(公告)日：2014-07-03

申请号：US13976262

申请日：2011-09-30

Applicant: Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F12/0866 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/262 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。

公开(公告)号：US08607129B2

公开(公告)日：2013-12-10

申请号：US13175500

申请日：2011-07-01

Applicant: Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

Inventor： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

公开(公告)号：US08583984B2

公开(公告)日：2013-11-12

申请号：US12976247

申请日：2010-12-22

Applicant: Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

Inventor： Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

IPC: H03M13/00

CPC classification number: G06F11/1076

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract translation: 提供了一种方法和装置，用于在数据块从易失性存储器传输到非易失性存储装置的同时使数据块的数据完整性检查得以实现。 数据完整性检查与直接内存访问操作和独立磁盘冗余阵列（RAID）操作一起执行。 此外，在向RAID系统的存储设备传输期间以及在RAID更新和RAID数据重建操作期间执行RAID中的校验块的数据完整性检查。

公开(公告)号：US20130007573A1

公开(公告)日：2013-01-03

申请号：US13175500

申请日：2011-07-01

Applicant: Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

Inventor： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract translation: 本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

公开(公告)号：US08275560B2

公开(公告)日：2012-09-25

申请号：US12557263

申请日：2009-09-10

Applicant: Sivakumar Radhakrishnan ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Looi ,  Yi-Feng Liu

Inventor： Sivakumar Radhakrishnan ,  Sin S. Tan ,  Stephan J. Jourdan ,  Lily P. Looi ,  Yi-Feng Liu

IPC: G01R15/00 ,  G01R19/00 ,  G01R21/00 ,  G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D50/20

Abstract: A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

Abstract translation: 一种能够以各种模式对片上系统进行功率测量的方法和系统。 在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。 这允许钩子或接口在外部访问片上系统进行测量。 例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量， 片上 片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。 另外，由于易于检测故障部件，所以能够提高SOC的整体产量。

公开(公告)号：US20120166909A1

公开(公告)日：2012-06-28

申请号：US12976247

申请日：2010-12-22

Applicant: Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

Inventor： Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

IPC: G11C29/00

CPC classification number: G06F11/1076

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract translation: 提供了一种方法和装置，用于在数据块从易失性存储器传输到非易失性存储装置的同时使数据块的数据完整性检查得以实现。 数据完整性检查与直接内存访问操作和独立磁盘冗余阵列（RAID）操作一起执行。 此外，在向RAID系统的存储设备传输期间以及在RAID更新和RAID数据重建操作期间执行RAID中的校验块的数据完整性检查。

公开(公告)号：US08122265B2

公开(公告)日：2012-02-21

申请号：US11648253

申请日：2006-12-29

Applicant: Sivakumar Radhakrishnan ,  Suneeta Sah ,  William H. Nale ,  Rami Naqib ,  Howard S. David ,  Rajat Agarwal

Inventor： Sivakumar Radhakrishnan ,  Suneeta Sah ,  William H. Nale ,  Rami Naqib ,  Howard S. David ,  Rajat Agarwal

IPC: G06F1/00

CPC classification number: G06F1/206 ,  G06F1/3203

Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括调度器，发射机，接收机和控制电路。 时间表调度要在芯片外部发送的信号，并且发送器在芯片外发送调度信号。 接收器接收包括具有与芯片外的温度有关的温度信息的信号的信号。 控制电路选择性地限制可以在一系列较小窗口内调度的多个命令，同时检查靠近包括许多较小窗口的较大窗口的结论的温度信息。 描述其他实施例。