公开(公告)号：US07958414B1

公开(公告)日：2011-06-07

申请号：US12888317

申请日：2010-09-22

Applicant: Ahmad R. Ansari ,  Ting Lu ,  Ismed D. Hartanto

Inventor： Ahmad R. Ansari ,  Ting Lu ,  Ismed D. Hartanto

IPC: G01R31/28 ,  G11C29/00 ,  G11C7/00 ,  H03K19/00 ,  G06F7/38

CPC classification number: H03K19/17768 ,  G11C7/20

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract translation: 公开了增强内部存储器的安全性的方法的实施例。 对于该方法的该实施例，应用特定块在功能模式下操作，并且启动应用特定块的复位。 响应于启动的复位，内部自​​检引擎至少进行一次写入，其中至少一次写入在复位模式期间覆盖存储在内部存储器中的数据。

公开(公告)号：US07788470B1

公开(公告)日：2010-08-31

申请号：US12057353

申请日：2008-03-27

Applicant: Kathryn S. Purcell ,  Ahmad R. Ansari ,  Gaurav Gupta

Inventor： Kathryn S. Purcell ,  Ahmad R. Ansari ,  Gaurav Gupta

IPC: G06F9/00

CPC classification number: G06F9/3855 ,  G06F9/3857 ,  G06F9/3877

Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract translation: 描述了用于支持指令执行不正常的方法和控制器。 微处理器经由控制器耦合到协处理器。 微处理器和控制器接收到指令。 分别与指令相关联的指示由微处理器产生，并且指令从第一个队列弹出，以供协处理器执行。 控制器包括第一队列和第二队列。 指令和索引在第一队列中排队，并且该第一排队包括将指令和与其相关联的索引转向相应的第一注册位置，同时保持指令和索引之间的关联。 相对于其中指令被接收到第一队列中的顺序，指令可以从第一队列中弹出。

公开(公告)号：US07730244B1

公开(公告)日：2010-06-01

申请号：US12057314

申请日：2008-03-27

Applicant: Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray

Inventor： Ahmad R. Ansari ,  Jeffery H. Appelbaum ,  Kam-Wing Li ,  James J. Murray

IPC: G06F13/00

CPC classification number: G06F13/28 ,  G06F13/385

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract translation: 描述突发命令的命令转换。 一个从属处理器本地总线（“PLB”）桥接器，嵌入在主机IC中的处理器块核心的一部分，具有允许访问交叉开关器件的数据大小阈值。 耦合到从属PLB桥的主设备具有多个命令总线宽度中的任何一个。 经由命令总线发出突发命令，该命令总线具有来自主PLB桥的主设备的多个命令总线宽度。 如果命令总线宽度不等于本地总线宽度，则突发命令将转换为从属处理器逻辑块的本机总线宽度。 如果突发命令的执行将超过数据大小阈值并且如果突发命令的执行不会超过数据大小阈值，则转换而不进行转换，则转换突发命令。

公开(公告)号：US07724028B1

公开(公告)日：2010-05-25

申请号：US12101375

申请日：2008-04-11

Applicant: Ahmad R. Ansari ,  Alex S. Warshofsky

Inventor： Ahmad R. Ansari ,  Alex S. Warshofsky

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/1774 ,  G06F1/10 ,  H03K19/17732

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract translation: 嵌入在主机IC中的ASIC块具有第一时钟域，其具有至少等于主机IC中的第二时钟域的第二频率的操作的第一操作频率，但是在ASIC块的外部。 第二个时钟域的FPGA逻辑与ASIC块接口; 并且位于主机集成电路中但在ASIC块外部的PLL被耦合以接收参考时钟信号并被配置为产生时钟信号。 时钟信号中的两个分别被发送到FPGA逻辑和ASIC块，以使它们相对于ASIC块在时间上比另一个稍早地产生，以补偿时钟插入延迟和时钟到输出 与FPGA逻辑相关的时间至少近似为零。

公开(公告)号：US07624209B1

公开(公告)日：2009-11-24

申请号：US10941240

申请日：2004-09-15

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi ,  Alex Scott Warshofsky

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi ,  Alex Scott Warshofsky

IPC: G06F5/06 ,  G06F13/00

CPC classification number: G06F13/4273

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract translation: 描述了在诸如具有嵌入式处理器的FPGA的电子设备中实现可变延迟数据传输的方法。 根据本发明的一个方面，一种方法包括以下步骤：为存储器控制器和外围设备之间的数据传送提供地址; 将地址有效信号耦合到外围设备; 在存储器控制器和外围设备之间传送数据; 并在存储器控制器处接收数据传送完成信号。 根据本发明的另一方面，描述了实现可变等待时间数据传输的集成电路。 集成电路包括外围设备; 耦合到所述外围设备的存储器控​​制器; 从所述存储器控制器耦合到所述外围设备的地址有效信号; 以及从外围设备耦合到存储器控制器的传送完成信号。

公开(公告)号：US07590823B1

公开(公告)日：2009-09-15

申请号：US10913231

申请日：2004-08-06

Applicant: Ahmad R. Ansari ,  Kathryn Story Purcell

Inventor： Ahmad R. Ansari ,  Kathryn Story Purcell

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F9/3877 ,  G06F9/30145

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract translation: 描述了通知处理器协处理器指令不能由协处理器执行的方法。 在可配置逻辑中实例化的协处理器被配置为执行协处理器指令的子集，排除未被实例化的用户选择的指令。 处理器经由控制器耦合到协处理器。 协处理器指令从处理器发送到控制器，控制器查询控制逻辑以确定协处理器是否被配置为执行协处理器指令。 如果控制位被设置为禁用指令或指令组，则协处理器指令不能由协处理器执行。

公开(公告)号：US07243212B1

公开(公告)日：2007-07-10

申请号：US10913991

申请日：2004-08-06

Applicant: Kathryn Story Purcell ,  Ahmad R. Ansari

Inventor： Kathryn Story Purcell ,  Ahmad R. Ansari

IPC: G06F15/16

CPC classification number: G06F9/3877 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3897 ,  G06F15/16

Abstract: Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not ready to execute the instruction. Initiation of execution of the instruction by the controller is done while continuing to indicate to the processor that the controller is not ready to execute the instruction.

Abstract translation: 描述了处理器和控制器之间的非锁步骤操作的方法和装置。 从处理器向控制器提供指令。 从控制器向处理器提供忙信号以指示控制器未准备好执行指令。 完成由控制器执行指令的启动，同时继续向处理器指示控制器尚未准备好执行指令。

公开(公告)号：US07007121B1

公开(公告)日：2006-02-28

申请号：US10084569

申请日：2002-02-27

Applicant: Ahmad R. Ansari ,  Mehul R. Vashi

Inventor： Ahmad R. Ansari ,  Mehul R. Vashi

IPC: G06F13/362 ,  G06F1/08 ,  G06F5/06

CPC classification number: G06F13/4273 ,  G06F13/364

Abstract: A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the devices that are part of the transaction. Additionally, the bus frequency is set according to the length of the bus between the devices that are a part of the transaction and, correspondingly, the expected amount of impedance there between. As a part of the present invention, a master seeking bus resources to initiate a transaction generates a bus request and a destination address to the bus arbiter so that it may determine a corresponding bus frequency in advance. Thereafter, the bus arbiter sets the bus frequency to a value that corresponds to the transaction that is about to take place thereon. Next, the bus arbiter issues a grant signal to enable the master to use the bus. Each slave device for a transaction then generates or receives sample cycle signals indicating when a signal should be read on the bus.

Abstract translation: 总线仲裁器控制包括多个总线主机和多个从机的系统中的总线频率。 总线频率根据作为交易一部分的设备的内部频率确定。 此外，总线频率根据总线在作为交易的一部分的设备之间的长度设置，相应地，其间的预期阻抗量设置。 作为本发明的一部分，寻求总线资源以启动事务的主机向总线仲裁器生成总线请求和目的地地址，使得它可以预先确定相应的总线频率。 此后，总线仲裁器将总线频率设置为与要在其上进行的事务相对应的值。 接下来，总线仲裁器发出授权信号，以使主机能够使用总线。 每个用于交易的从设备都生成或接收采样周期信号，指示何时应在总线上读取信号。

公开(公告)号：US06665749B1

公开(公告)日：2003-12-16

申请号：US09375876

申请日：1999-08-17

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F1300

CPC classification number: G06F13/1678

Abstract: The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the vector transfer unit and the memory. The external bus includes a system command bus that is used to transmit a data transfer command. The command is based on a corresponding vector transfer instruction in the application program, such as load vector data or store vector data. The commands for transferring the data elements include a burst read command and a burst write command. A variable number of data elements may be transferred, according to the user's requirements. The system command bus is also capable of transmitting a packing ratio that indicates the number of data elements that fit in the width of the external bus. This allows the entire bandwidth of the external bus to be used during vector data transfers. The external bus also includes an address bus for transmitting the starting address, the length, and the stride of the vector data to be transferred. This allows an external agent to properly unpack the data elements on their correct boundary. Input and output validity signals provide an indication of the validity of the data elements transferred as well as to indicate when the transfer of the data elements is interrupted. A system clock signal is also included in the external bus to indicate the transfer rate of the data elements.

Abstract translation: 本发明提供一种用于数据处理系统的总线架构，其使用向量传送单元（VTU）改进向量数据的传送。 外部总线耦合在矢量传送单元和存储器之间。 外部总线包括用于发送数据传输命令的系统命令总线。 该命令基于应用程序中的相应向量传输指令，如加载向量数据或存储向量数据。 用于传送数据元素的命令包括突发读取命令和突发写入命令。 可以根据用户的要求传送可变数量的数据元素。 系统命令总线还能够发送指示适合外部总线宽度的数据元素的数量的打包率。 这允许在矢量数据传输期间使用外部总线的整个带宽。 外部总线还包括用于发送要传送的矢量数据的起始地址，长度和步幅的地址总线。 这允许外部代理在正确的边界上正确地解包数据元素。 输入和输出有效性信号提供所传送的数据元素的有效性的指示以及指示何时中断数据元素的传送。 外部总线中还包括系统时钟信号，以指示数据元素的传输速率。

公开(公告)号：US06553486B1

公开(公告)日：2003-04-22

申请号：US09376125

申请日：1999-08-17

Applicant: Ahmad R. Ansari

Inventor： Ahmad R. Ansari

IPC: G06F1200

CPC classification number: G06F9/4843

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor by one or more application programs in a computer system. A compiler identifies the use of vector data in the application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. The compiler also schedules transfers of portions of the vector data required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers based on configuration information including the number of vectors buffers required by an application program and the size required for each vector buffer. The vector buffers are allocated for exclusive use by an application program that is executing in the data processor. During a context switch between application programs, a synchronization instruction is used to allow the instructions issued by one application program to finish before any transfer instructions issued by the second application program may begin. Instructions for indicating whether the vector buffer pool is available for use are also included.

Abstract translation: 一种矢量传送单元，用于通过计算机系统中的一个或多个应用程序来处理存储器和数据处理器之间的矢量数据传输。 编译器识别应用程序中矢量数据的使用，并实现一个或多个矢量指令，用于在用于对矢量数据执行计算的存储器和寄存器之间传送矢量数据。 编译器还调度计算中所需的矢量数据的部分的传送，使得在矢量数据的后续部分被传送的同时执行矢量数据的一部分上的计算。 基于包括应用程序所需的向量缓冲器的数量和每个向量缓冲器所需的大小的配置信息将向量缓冲池划分成一个或多个向量缓冲器。 向量缓冲区被分配给正在数据处理器中执行的应用程序专用。 在应用程序之间的上下文切换期间，使用同步指令来允许由一个应用程序发出的指令在由第二应用程序发出的任何传输指令开始之前完成。 还包括指示是否可以使用向量缓冲池的说明。