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公开(公告)号：US10700264B2
公开(公告)日：2020-06-30
申请号：US16511862
申请日：2019-07-15
发明人： Wei-Hao Liao , Chih-Wei Lu , Hsi-Wen Tien , Pin-Ren Dai , Chung-Ju Lee
摘要： A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.
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公开(公告)号：US20200098978A1
公开(公告)日：2020-03-26
申请号：US16510296
申请日：2019-07-12
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
摘要： A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.
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公开(公告)号：US10355198B2
公开(公告)日：2019-07-16
申请号：US15811405
申请日：2017-11-13
发明人： Wei-Hao Liao , Chih-Wei Lu , Hsi-Wen Tien , Pin-Ren Dai , Chung-Ju Lee
摘要： A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.
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公开(公告)号：US10270028B1
公开(公告)日：2019-04-23
申请号：US15813055
申请日：2017-11-14
发明人： Hsi-Wen Tien , Chih-Wei Lu , Wei-Hao Liao , Pin-Ren Dai , Chung-Ju Lee
摘要： A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.
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公开(公告)号：US12069958B2
公开(公告)日：2024-08-20
申请号：US18312372
申请日：2023-05-04
发明人： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Sheng-Chih Lai , Han-Ting Tsai , Chung-Te Lin
CPC分类号： H10N50/01 , G11C11/161 , H10B61/20 , H10N50/10 , H10N50/80
摘要： A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.
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公开(公告)号：US20240258117A1
公开(公告)日：2024-08-01
申请号：US18586989
申请日：2024-02-26
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih Wei Lu , Pin-Ren Dai , Chung-Ju Lee
IPC分类号： H01L21/3213 , H01L21/033 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/32136 , H01L21/76816 , H01L21/76832 , H01L23/5226 , H01L23/53209
摘要： A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.
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公开(公告)号：US20240120200A1
公开(公告)日：2024-04-11
申请号：US18543432
申请日：2023-12-18
发明人： Hsi-Wen Tien , Wei-Hao Liao , Pin-Ren Dai , Chih Wei Lu , Chung-Ju Lee
IPC分类号： H01L21/033 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/76877
摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
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公开(公告)号：US11849645B2
公开(公告)日：2023-12-19
申请号：US17833688
申请日：2022-06-06
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
摘要： An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
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公开(公告)号：US20220376169A1
公开(公告)日：2022-11-24
申请号：US17814917
申请日：2022-07-26
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih Wei Lu , Pin-Ren Dai , Chung-Ju Lee
摘要： A memory device includes a bottom electrode, a tunneling junction disposed over the bottom electrode, and a top electrode disposed over the tunneling junction. The top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer. The first and second top electrode layers include different material compositions. The first top electrode layer is thinner than the tunneling junction, and the second top electrode layer is thicker than the tunneling junction.
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公开(公告)号：US11355701B2
公开(公告)日：2022-06-07
申请号：US17001282
申请日：2020-08-24
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
摘要： An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
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