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公开(公告)号：US11616055B2
公开(公告)日：2023-03-28
申请号：US17095149
申请日：2020-11-11
发明人： Chun-Yao Ku , Wen-Hao Chen , Kuan-Ting Chen , Ming-Tao Yu , Jyun-Hao Chang
IPC分类号： H01L27/00 , H01L27/02 , G06F30/392 , H01L23/538 , G06F30/20 , H01L51/44
摘要： A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.
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公开(公告)号：US11604915B2
公开(公告)日：2023-03-14
申请号：US17231194
申请日：2021-04-15
发明人： Hung-Chih Ou , Kuo-Fu Lee , Wen-Hao Chen , Keh-Jeng Chang , Hsiang-Ho Chang
IPC分类号： G06F30/398 , G06F119/18
摘要： A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
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公开(公告)号：US11087061B2
公开(公告)日：2021-08-10
申请号：US16826018
申请日：2020-03-20
发明人： Hung-Chih Ou , Wen-Hao Chen
IPC分类号： G06F30/392 , G06F30/3953 , G06F30/398 , G06F30/3312 , G06F119/12
摘要： A method, a non-transitory computer-readable storage medium and a system for a design layout are provided. The method includes: receiving a design layout including a first cell and a second cell; providing a conductive member electrically connected between the first cell and the second cell, the conductive member including a first conductive line and a second conductive line parallel to the first conductive line; determining a first merging point in the first conductive line between the first cell and the second cell; and electrically connecting the first conductive line to the second conductive line at the first merging point.
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24.发明授权公开(公告)号：US09477803B2
公开(公告)日：2016-10-25
申请号：US14446752
申请日：2014-07-30
发明人： Chung-Hsing Wang , King-Ho Tam , Yen-Pin Chen , Wen-Hao Chen , Chung-Kai Lin , Chih-Hsiang Yao
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5009 , G06F17/5081
摘要： A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.
摘要翻译： 公开了一种生成对应于预定制造工艺的技术文件的方法。 该方法包括基于一个或多个样本集成电路芯片的测量来确定用于通过预定制造工艺制造的用于建模待制造的后端层（BEOL）特征层的电特性的典型值和角度变化值 通过预定的制造工艺制造。 基于角度变化值和缩放因子计算减小的变化值。 技术文件是基于典型值和减小的变化值生成的。
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公开(公告)号：US09064081B1
公开(公告)日：2015-06-23
申请号：US14103558
申请日：2013-12-11
发明人： Meng-Kai Hsu , Chi-Yeh Yu , Yuan-Te Hou , Wen-Hao Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.
摘要翻译： 提供了一种线路布线方法。 该方法包括获得单元格布局的数据，生成单元布局的第一数据库，为第一数据库中的每个单元识别第一数据库中的单元和另一单元是否在引脚层中可路由，以及生成第二数据库 对于可路由的单元。
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公开(公告)号：US12014131B2
公开(公告)日：2024-06-18
申请号：US18337245
申请日：2023-06-19
发明人： Sheng-Hsiung Chen , Wen-Hao Chen , Hung-Chih Ou , Chun-Yao Ku , Shao-Huan Wang
IPC分类号： G06F30/30 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F30/398 , G06F30/392 , G06F115/06 , G06F119/06 , G06F119/12
CPC分类号： G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F30/392 , G06F2115/06 , G06F2119/06 , G06F2119/12
摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
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公开(公告)号：US20230205974A1
公开(公告)日：2023-06-29
申请号：US18176701
申请日：2023-03-01
发明人： Hung-Chih Ou , Kuo-Fu Lee , Wen-Hao Chen , Keh-Jeng Chang , Hsiang-Ho Chang
IPC分类号： G06F30/398
CPC分类号： G06F30/398 , G06F2119/18
摘要： A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
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公开(公告)号：US20220335196A1
公开(公告)日：2022-10-20
申请号：US17231194
申请日：2021-04-15
发明人： Hung-Chih Ou , Kuo-Fu Lee , Wen-Hao Chen , Keh-Jeng Chang , Hsiang-Ho Chang
IPC分类号： G06F30/398
摘要： A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
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公开(公告)号：US10990745B2
公开(公告)日：2021-04-27
申请号：US16559534
申请日：2019-09-03
发明人： Sheng-Hsiung Chen , Shao-Huan Wang , Wen-Hao Chen , Chun-Yao Ku , Hung-Chih Ou
IPC分类号： G06F17/50 , G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G03F1/70 , G03F1/36 , G06F30/394 , G06F115/06 , G06F119/06 , G06F119/12 , G06F30/392
摘要： An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.
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公开(公告)号：US20210117605A1
公开(公告)日：2021-04-22
申请号：US17129195
申请日：2020-12-21
发明人： Po-Chia Lai , Kuo-Ji Chen , Wen-Hao Chen , Wun-Jie Lin , Yu-Ti Su , Mohammed Rabiul Islam , Shu-Yi Ying , Stefan Rusu , Kuan-Te Li , David Barry Scott
IPC分类号： G06F30/392 , H01L27/02 , G01R31/50 , G06F30/327 , G06F30/367 , G06F30/398
摘要： An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
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