公开(公告)号：US20210327525A1

公开(公告)日：2021-10-21

申请号：US17364647

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/12 ,  G11C29/26 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US11087857B2

公开(公告)日：2021-08-10

申请号：US16192796

申请日：2018-11-15

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/12 ,  G11C29/26 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US10134483B2

公开(公告)日：2018-11-20

申请号：US15275694

申请日：2016-09-26

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Sumant Dinkar Kale

IPC: G11C29/44 ,  G11C29/12 ,  G06F11/20 ,  G11C29/00 ,  G01R31/28

Abstract: A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.

公开(公告)号：US09318222B2

公开(公告)日：2016-04-19

申请号：US14108489

申请日：2013-12-17

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Raghavendra Prasad KS ,  Harsharaj Ellur

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.

Abstract translation: 内置自检（BIST）电路，用于测试集成电路上的一个或多个存储器块。 一个或多个存储器块还包括第一存储器块和第二存储器块A，内置软修复控制器（BISoR）被提供以软修复一个或多个存储器块。 配置BISoR的BIST电路配置为在执行第二个内存块的测试和软修复之前测试和软修复第一个内存块。

公开(公告)号：US20150100608A1

公开(公告)日：2015-04-09

申请号：US14506216

申请日：2014-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Karthik Srinivasan ,  Neel Talakshi Gala

IPC: H03K19/00 ,  G06F7/50 ,  G06F7/52 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17752 ,  H03K19/17764

Abstract: Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.

Abstract translation: 在运行时重新配置ASIC的方法，而不使用电压超标。 识别ASIC中的一组逻辑的功能关键性。 然后，基于功能关键性将该组逻辑分类为一组区域，该区域集合的每个区域具有目标误差阈值。 此外，每个区域在运行时基于功能关键性进行功率门控，使得在不使用电压超标的情况下实现目标误差阈值。

公开(公告)号：US20250028476A1

公开(公告)日：2025-01-23

申请号：US18909050

申请日：2024-10-08

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan

IPC: G06F3/06

Abstract: An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.

公开(公告)号：US12147697B2

公开(公告)日：2024-11-19

申请号：US17900551

申请日：2022-08-31

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan

IPC: G06F12/00 ,  G06F3/06

Abstract: An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.

公开(公告)号：US12009045B2

公开(公告)日：2024-06-11

申请号：US17843897

申请日：2022-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan Varadarajan ,  Varun Singh

IPC: G11C29/44 ,  G11C17/16 ,  G11C29/14 ,  G11C29/42

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C29/14 ,  G11C29/42

Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

公开(公告)号：US20240120016A1

公开(公告)日：2024-04-11

申请号：US18392740

申请日：2023-12-21

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

CPC classification number: G11C29/16 ,  G01R31/318594 ,  G01R31/318597 ,  G11C29/022 ,  G11C29/023 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US20230324456A1

公开(公告)日：2023-10-12

申请号：US17877607

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Benjamin Niewenhuis

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31703 ,  G01R31/3177

Abstract: An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.