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公开(公告)号：US10763748B2
公开(公告)日：2020-09-01
申请号：US15995331
申请日：2018-06-01
Applicant: Texas Instruments Incorporated
Inventor： Ivan Shumkov , Erich Bayer , Joerg Kirchner , Ruediger Ganz , Michael Lueders , Martin Priess , Nicola Rasera
IPC: H02M3/158
Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node. For boost operation in a second mode, the switching circuit alternates between connecting the inductor and the capacitor in series between the input node and the reference node to discharge the inductor and charge the capacitor in a first boost mode phase, and connecting the inductor between the input node and the reference node to charge the inductor and connecting the capacitor between the first output node and the reference node to discharge the capacitor to deliver power to the output node in a second boost mode phase.
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公开(公告)号：US20200274530A1
公开(公告)日：2020-08-27
申请号：US16731847
申请日：2019-12-31
Applicant: Texas Instruments Incorporated
Inventor： Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
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公开(公告)号：US10355591B2
公开(公告)日：2019-07-16
申请号：US15658667
申请日：2017-07-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Maurizio Granato , Giovanni Frattini , Pietro Giannelli , Michael Lueders , Christian Rott
Abstract: Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the ends of the switching circuitry and corresponding output nodes, and with a flying capacitor coupled across interior switches of the switching circuitry and a second capacitor coupled across the ends of the switching circuitry. A control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. The output inductors are wound on a common core in certain examples.
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公开(公告)号：US20190052173A1
公开(公告)日：2019-02-14
申请号：US15995331
申请日：2018-06-01
Applicant: Texas Instruments Incorporated
Inventor： Ivan Shumkov , Erich Bayer , Joerg Kirchner , Ruediger Ganz , Michael Lueders , Martin Priess , Nicola Rasera
IPC: H02M3/158
CPC classification number: H02M3/1582
Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node. For boost operation in a second mode, the switching circuit alternates between connecting the inductor and the capacitor in series between the input node and the reference node to discharge the inductor and charge the capacitor in a first boost mode phase, and connecting the inductor between the input node and the reference node to charge the inductor and connecting the capacitor between the first output node and the reference node to discharge the capacitor to deliver power to the output node in a second boost mode phase.
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公开(公告)号：US20170331376A1
公开(公告)日：2017-11-16
申请号：US15658667
申请日：2017-07-25
Inventor： Maurizio Granato , Giovanni Frattini , Pietro Giannelli , Michael Lueders , Christian Rott
CPC classification number: H02M3/158 , G05F1/565 , G05F1/573 , G05F1/595 , H02M3/142 , H02M3/33569 , H02M2001/0003
Abstract: Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the ends of the switching circuitry and corresponding output nodes, and with a flying capacitor coupled across interior switches of the switching circuitry and a second capacitor coupled across the ends of the switching circuitry. A control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. The output inductors are wound on a common core in certain examples.
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Patent Agency Ranking
公开(公告)号：US20240429233A1
公开(公告)日：2024-12-26
申请号：US18828356
申请日：2024-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Tipirneni , Maik Peter Kaufmann , Michael Lueders , Jungwoo Joh
IPC: H01L27/06 , H01L21/8252 , H01L29/20 , H01L29/66 , H01L29/778 , H02M3/156 , H03K3/037
Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.
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公开(公告)号：US20240146298A1
公开(公告)日：2024-05-02
申请号：US17977822
申请日：2022-10-31
Applicant: Texas Instruments Incorporated
Inventor： Raveesh Magod Ramakrishna , Maik Peter Kaufmann , Michael Lueders , Johan Strydom , Stefan Herzer
IPC: H03K17/687 , H03K5/13
CPC classification number: H03K17/6871 , H03K5/13 , H03K2005/00019
Abstract: In described examples, an integrated circuit includes first and second current sources, first and second switches, a dV/dt phase detector, a control circuit, and source, gate, and drain terminals for coupling to, respectively, a source, gate, and drain of a power FET. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV/dt phase detector detects a dV/dt phase of the power FET and outputs to the control circuit. The control circuit controls the first and second switches to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV/dt phase detector indicating the dV/dt phase has started, opening the first switch, and closing the second switch.
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公开(公告)号：US20230336167A1
公开(公告)日：2023-10-19
申请号：US18212213
申请日：2023-06-21
Applicant: Texas Instruments Incorporated
Inventor： Gaetano Maria Walter Petrina , Michael Lueders , Nicola Rasera
IPC: H03K5/1534 , H02M1/08 , H03K5/13 , H02M1/38
CPC classification number: H03K5/1534 , H02M1/08 , H03K5/13 , H02M1/38 , H03K2005/00078
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.
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公开(公告)号：US11489441B2
公开(公告)日：2022-11-01
申请号：US16890537
申请日：2020-06-02
Applicant: Texas Instruments Incorporated
Inventor： Maik Peter Kaufmann , Michael Lueders , Bernhard Wicht
Abstract: Reference voltage generation circuits and related methods are disclosed. An example reference voltage generation circuit includes a voltage generating circuit including an enhancement mode (E-mode) gallium nitride (GaN) transistor, the voltage generating circuit to, in response to a first clock signal having a first phase, generate a first voltage associated with the E-mode GaN transistor, and, in response to a second clock signal having a second phase different from the first phase, generate a second voltage associated with the E-mode GaN transistor, and a switching capacitor circuit coupled to the voltage generating circuit, the switching capacitor circuit to generate a reference voltage based on a difference between the first voltage and the second voltage.
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公开(公告)号：US20220244638A1
公开(公告)日：2022-08-04
申请号：US17512959
申请日：2021-10-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hidetoshi Inoue , Kenji Kawano , Yuki Sato , Takafumi Ando , Michael Lueders , Stefan Herzer , Jeffrey Morroni
IPC: G03F7/00 , H01L21/027
Abstract: A permanent resist, such as TMMF, is used when patterning conductive material on a substrate, enabling lines that have a higher line-to-space ratio (L/S) or a higher aspect ratio (T/L) or both. Pattern density can thus be increased, allowing for improved performance (e.g., greater efficiency, in the case of transformer coil patterning) and greater heat dissipation. As examples, the permanent-resist-based patterning fabrication methods can be used to create transformer coils within an integrated circuit (IC) module, or a routable lead frame for one or more IC dies.
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