公开(公告)号：US20160293596A1

公开(公告)日：2016-10-06

申请号：US14673844

申请日：2015-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract translation: 在III-N层堆叠中包含增强型GaN FET的半导体器件包括低掺杂GaN层，在低掺杂GaN层上包括铝的阻挡层，在阻挡层上包括铟的应力层，以及帽 层包括在应力层上的铝。 栅极凹槽延伸穿过覆盖层和应力层，但不穿过阻挡层。 半导体器件通过用高温MOCVD工艺形成阻挡层而形成，通过低温MOCVD工艺形成应力层，并用低温MOCVD工艺形成覆盖层。 栅极凹部通过包括第一蚀刻步骤以去除覆盖层的两步蚀刻工艺形成，以及第二蚀刻步骤以去除应力层。

公开(公告)号：US09093301B2

公开(公告)日：2015-07-28

申请号：US13789949

申请日：2013-03-08

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8236 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US08933461B2

公开(公告)日：2015-01-13

申请号：US13886410

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L31/0256 ,  H01L21/336 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66477 ,  H01L29/7786

Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.

Abstract translation: 半导体器件包括在增强型GaN FET的栅极节点和半导体器件的栅极端子之间串联电耦合的耗尽型GaN FET的增强型GaN FET。 耗尽型GaN FET的栅极节点电耦合到增强型GaNFET的源极节点。 所述增强型GaN FET的源节点电耦合到半导体器件的源极端子，增强型GaNFET的漏极节点电耦合到所述半导体器件的漏极端子，并且耗尽模式的漏极节点 GaN FET电耦合到半导体器件的栅极端子。

公开(公告)号：US08829613B1

公开(公告)日：2014-09-09

申请号：US13886709

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L29/76

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US08759879B1

公开(公告)日：2014-06-24

申请号：US13886688

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar ,  Jungwoo Joh

IPC: H01L31/109

CPC classification number: H01L29/2003 ,  H01L29/063 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7786

Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.

Abstract translation: 包含GaN FET的半导体器件在低缺陷层的至少一个III-N半导体层和阻挡层下面的电隔离层中具有n型掺杂。 n型掺杂的片电荷载流子密度为二维电子气的片电荷载流子密度的1〜200％。

公开(公告)号：US20210242200A1

公开(公告)日：2021-08-05

申请号：US17234385

申请日：2021-04-19

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/306

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

公开(公告)号：US10680093B2

公开(公告)日：2020-06-09

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US10381456B2

公开(公告)日：2019-08-13

申请号：US15587021

申请日：2017-05-04

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/778 ,  H01L29/66 ,  H01L23/535 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.

公开(公告)号：US09882041B1

公开(公告)日：2018-01-30

申请号：US15353857

申请日：2016-11-17

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/3083 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/66462

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US09741557B1

公开(公告)日：2017-08-22

申请号：US15191500

申请日：2016-06-23

Applicant: Texas Instruments Incorporated

Inventor： Nicholas Stephen Dellas ,  Naveen Tipirneni ,  Dong Seup Lee

IPC: H01L29/02 ,  H01L21/02 ,  H01L29/20 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/0228 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78606

Abstract: A semiconductor device has a substrate with a semiconductor material. The semiconductor device includes a field effect transistor in and on the semiconductor material. The field effect transistor has a gate dielectric layer over the semiconductor material of the semiconductor device, and a gate over the gate dielectric layer. The gate dielectric layer includes a layer of nitrogen-rich silicon nitride immediately over the region for the channel, and under the gate.