公开(公告)号：US20210327829A1

公开(公告)日：2021-10-21

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L33/62 ,  H01L23/00 ,  H01L33/00

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20210175195A1

公开(公告)日：2021-06-10

申请号：US17028353

申请日：2020-09-22

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yong Xie ,  Rajen Manicon Murugan ,  Woochan Kim

IPC: H01L23/00 ,  H01L25/16

Abstract: In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.

公开(公告)号：US20240313404A1

公开(公告)日：2024-09-19

申请号：US18429140

申请日：2024-01-31

Applicant: Texas Instruments Incorporated

Inventor： Harshpreet Singh Phull Bakshi ,  Rajen Manicon Murugan ,  Sylvester Ankamah-Kusi

IPC: H01Q9/04 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q1/42

CPC classification number: H01Q9/0407 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/422

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate has first, second, and third levels including respective dielectric layers and conductive features, the first level including a first trace layer with an antenna and a first via layer with a portion of a ground wall laterally spaced outward from and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall, the semiconductor die attached to the first level of the multilevel package substrate, and the package structure including a molding compound enclosing the semiconductor die and extending on a side of the antenna, where the package structure mold compound maters and thickness can be tuned for improved performance.

公开(公告)号：US20240178154A1

公开(公告)日：2024-05-30

申请号：US18070708

申请日：2022-11-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen ,  Jaimal Mallory Williamson

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a molded package structure, where the multilevel package substrate has opposite first and second substrate sides, first and second conductive pads spaced apart from one another along the first substrate side, and a conductive substrate terminal that is exposed along the second substrate side and is electrically coupled to the second conductive pad. The semiconductor die is attached to the first substrate side and has opposite first and second die sides, and a die terminal along the first die side, the die terminal electrically coupled to the first conductive pad. The molded has a package side, a metal shield along the package side, and a conductive package via that extends through the molded package structure and electrically couples the metal shield to the second conductive pad.

公开(公告)号：US11978699B2

公开(公告)日：2024-05-07

申请号：US17406150

申请日：2021-08-19

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L21/6835 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2224/81385 ,  H01L2224/81815

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US20240112997A1

公开(公告)日：2024-04-04

申请号：US18482944

申请日：2023-10-09

Applicant: Texas Instruments Incorporated

Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/16227

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

公开(公告)号：US20230317644A1

公开(公告)日：2023-10-05

申请号：US17710931

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01Q1/38 ,  H01Q1/22 ,  H01Q3/36 ,  H01Q21/06 ,  H01Q3/44 ,  H01Q5/371 ,  H01Q1/42 ,  H01Q15/00

CPC classification number: H01L23/66 ,  H01L24/16 ,  H01L24/13 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49541 ,  H01Q1/38 ,  H01Q1/2283 ,  H01Q3/36 ,  H01Q21/065 ,  H01Q3/44 ,  H01Q5/371 ,  H01Q1/422 ,  H01Q15/0026 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/32245 ,  H01L2224/16245 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2924/182 ,  H01Q21/10

Abstract: Described examples include an apparatus having a first antenna and a second antenna formed in a first layer on a first surface of a multilayer package substrate, the multilayer package substrate having layers including patterned conductive portions and dielectric portions, the multilayer package substrate having a second surface opposite the first surface. The apparatus also has an isolation wall formed in the multilayer package substrate formed in at least a second and a third layer in the multilayer package substrate and a semiconductor die mounted to the first surface of the multilayer package substrate spaced from and coupled to the first antenna and the second antenna.

公开(公告)号：US20230268259A1

公开(公告)日：2023-08-24

申请号：US17677042

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Guangxu Li ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L24/16 ,  H01L21/4857 ,  H01L21/56 ,  H01L24/81 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/81007 ,  H01L2224/32227 ,  H01L2224/8385

Abstract: An electronic device with a multilevel package substrate having multiple levels including a first level having conductive leads and a final level having conductive landing areas along a side, as well as a die mounted to the multilevel package substrate and having conductive terminals electrically coupled to respective ones of the conductive leads, and a package structure that encloses the die and a portion of the multilevel package substrate, where the multilevel package substrate has a conductive elevated trace layer with a confinement feature that extends outward from the side of the final level along a third direction that is orthogonal to the first and second directions, the confinement feature having a sidewall configured to laterally confine one of a solder, an adhesive, a side of a passive component, and a side of the die.

公开(公告)号：US11600555B2

公开(公告)日：2023-03-07

申请号：US17233205

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

公开(公告)号：US20230021179A1

公开(公告)日：2023-01-19

申请号：US17379549

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen

IPC: H01L49/02 ,  H01F17/00 ,  H05K3/46 ,  H05K1/11 ,  H02M3/158

Abstract: A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.