公开(公告)号：US11239851B2

公开(公告)日：2022-02-01

申请号：US16997975

申请日：2020-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Kumar Reddy Naru ,  Anand Jerry George ,  Shagun Dusad ,  Visvesvaraya Appala Pentakota

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/18

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

公开(公告)号：US10985708B2

公开(公告)日：2021-04-20

申请号：US15980771

申请日：2018-05-16

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

IPC: H03F1/56 ,  H03F3/45 ,  H03G1/00 ,  H03G3/30 ,  G01S7/52

Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

公开(公告)号：US10903845B2

公开(公告)日：2021-01-26

申请号：US16941718

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03M1/14 ,  H03M1/12 ,  H03M1/00 ,  H03K19/20

Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input signal, a first current terminal, and a second current terminal coupled to the control terminal of the second transistor and the second current terminal of the third transistor; a seventh transistor having a control terminal coupled to the control terminal of the second transistor, a first current terminal coupled to a second voltage supply, and a second current terminal coupled to the first current terminal of the fifth transistor; an eighth transistor having a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second voltage supply, and a second current terminal coupled to the first current terminal of the sixth transistor; a ninth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal coupled to the second current terminal of the second transistor and the second current terminal of the fifth transistor; and a tenth transistor having a control terminal coupled to the second input signal, a first current terminal coupled to the second terminal of the fourth transistor, and a second current terminal coupled to the second current terminal of the third transistor.

公开(公告)号：US10778243B2

公开(公告)日：2020-09-15

申请号：US16860145

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala Pentakota ,  Rishi Soundararajan ,  Shagun Dusad ,  Chirag Chandrahas Shetty

IPC: H03M1/38 ,  H03K5/24 ,  H03M1/00 ,  H03K19/20 ,  H03M1/12 ,  H03M1/14

Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.

公开(公告)号：US10686461B1

公开(公告)日：2020-06-16

申请号：US16234685

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya KrishnaSwamy Nurani ,  Arun Mohan ,  Shagun Dusad ,  Neeraj Shrivastava

IPC: H03M1/06 ,  H03F1/32 ,  H03F3/45 ,  H04B1/38

Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

公开(公告)号：US10476542B1

公开(公告)日：2019-11-12

申请号：US16274621

申请日：2019-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Neeraj Shrivastava ,  Rajendrakumar Joish ,  Shagun Dusad ,  Visvesvaraya Pentakota

IPC: H04B1/04 ,  H04B1/18 ,  H03K17/94 ,  H03K19/173

Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.

公开(公告)号：US10341082B1

公开(公告)日：2019-07-02

申请号：US15906000

申请日：2018-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Shagun Dusad ,  Visvesvaraya Pentakota ,  Srinivas Kumar Reddy Naru ,  Sarma Sundareswara Gunturi ,  Nagalinga Swamy Basayya Aremallapur

IPC: H04L7/00 ,  H03K5/14 ,  H03K5/00 ,  H04L9/32

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

公开(公告)号：US10320405B2

公开(公告)日：2019-06-11

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20250096813A1

公开(公告)日：2025-03-20

申请号：US18966610

申请日：2024-12-03

Applicant: Texas Instruments Incorporated

Inventor： Sai Aditya Nurani ,  Rishi Soundararajan ,  Nithin Gopinath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/12 ,  H03M1/44 ,  H03M1/50 ,  H03M1/78

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

公开(公告)号：US20240113678A1

公开(公告)日：2024-04-04

申请号：US18531264

申请日：2023-12-06

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Vysakh Karthikeyan ,  Naveen Mahadev ,  Rafi Mahammad

IPC: H03H7/42 ,  H01F27/28 ,  H03H7/00

CPC classification number: H03H7/42 ,  H01F27/28 ,  H03H7/004 ,  H03H7/38

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.