公开(公告)号：US11680984B1

公开(公告)日：2023-06-20

申请号：US17683126

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Aravinda Acharya ,  Nikita Naresh

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3177

CPC classification number: G01R31/318536 ,  G01R31/3177 ,  G01R31/31727 ,  G01R31/31926

Abstract: In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.

公开(公告)号：US11604221B1

公开(公告)日：2023-03-14

申请号：US17566190

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

IPC: G01R31/317 ,  G01R31/3177 ,  G11C19/28 ,  H03K19/20

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

公开(公告)号：US20220091919A1

公开(公告)日：2022-03-24

申请号：US17543827

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/14 ,  G11C29/50 ,  G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  G11C29/56

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

公开(公告)号：US11073553B2

公开(公告)日：2021-07-27

申请号：US16185629

申请日：2018-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan

IPC: G11C29/42 ,  G11C29/36 ,  G06F11/10 ,  G01R31/3177 ,  G01R31/317 ,  G11C29/56

Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.

公开(公告)号：US09535123B2

公开(公告)日：2017-01-03

申请号：US14985699

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Rajesh Kumar Mittal ,  Wilson Pradeep ,  Vivek Singhal

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/317 ,  G01R31/44

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/318538 ,  G01R31/318563 ,  G01R31/318575

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract translation: 扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。 通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数 时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中 以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。