公开(公告)号：US11680984B1

公开(公告)日：2023-06-20

申请号：US17683126

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Aravinda Acharya ,  Nikita Naresh

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3177

CPC classification number: G01R31/318536 ,  G01R31/3177 ,  G01R31/31727 ,  G01R31/31926

Abstract: In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.

公开(公告)号：US20220091919A1

公开(公告)日：2022-03-24

申请号：US17543827

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/14 ,  G11C29/50 ,  G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  G11C29/56

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

公开(公告)号：US11521698B2

公开(公告)日：2022-12-06

申请号：US17002813

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Prathyusha Teja Inuganti ,  Rakesh Channabasappa Yaraduyathinahalli ,  Aravinda Acharya ,  Jasbir Singh ,  Naveen Ambalametil Narayanan

IPC: G11C29/38 ,  G11C17/00 ,  G11C29/00 ,  G11C11/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C14/00 ,  G06F12/06 ,  G06F9/4401

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US11194645B2

公开(公告)日：2021-12-07

申请号：US16737548

申请日：2020-01-08

Applicant: Texas Instruments Incorporated

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/3185 ,  G01R31/317 ,  G11C29/56 ,  G11C29/12 ,  G11C29/20 ,  G11C29/32 ,  G11C29/50 ,  G11C29/14 ,  G06F11/26 ,  G01R31/14 ,  G11C29/10 ,  G11C29/36

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

公开(公告)号：US11768726B2

公开(公告)日：2023-09-26

申请号：US17543827

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/14 ,  G11C29/50 ,  G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  G11C29/56 ,  G06F11/26 ,  G01R31/14 ,  G11C29/10 ,  G11C29/36

CPC classification number: G06F11/0757 ,  G01R31/31725 ,  G01R31/31858 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/20 ,  G11C29/32 ,  G11C29/50012 ,  G11C29/56012 ,  G01R31/14 ,  G06F11/261 ,  G11C29/10 ,  G11C29/36 ,  G11C2029/1204 ,  G11C2029/3202

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

公开(公告)号：US10818374B2

公开(公告)日：2020-10-27

申请号：US16271660

申请日：2019-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Prathyusha Teja Inuganti ,  Rakesh Channabasappa Yaraduyathinahalli ,  Aravinda Acharya ,  Jasbir Singh ,  Naveen Ambalametil Narayanan

IPC: G11C29/38 ,  G11C17/00 ,  G11C29/00 ,  G11C11/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C14/00 ,  G06F12/06 ,  G06F9/4401

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US10579454B2

公开(公告)日：2020-03-03

申请号：US15630516

申请日：2017-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravinda Acharya ,  Wilson Pradeep ,  Prakash Narayanan

IPC: G06F11/07 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/14 ,  G11C29/50 ,  G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  G11C29/56 ,  G06F11/26 ,  G01R31/14 ,  G11C29/10 ,  G11C29/36

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.