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    Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal
    21.
    发明授权
    Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal 有权
    半导体存储器件根据第一内部时钟信号和第二内部时钟信号输出数据

    公开(公告)号：US06388945B2

    公开(公告)日：2002-05-14

    申请号：US09811521

    申请日：2001-03-20

    申请人： Tadao Aikawa

    发明人： Tadao Aikawa

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A semiconductor memory device outputs data in synchronization with an external clock signal. The semiconductor memory device comprises a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal; a delay circuit delaying the external clock signal; a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.

    摘要翻译： 半导体存储器件与外部时钟信号同步地输出数据。 半导体存储器件包括：第一分频器，分配提供给其的外部时钟信号的频率，以产生第一内部时钟信号; 延迟电路延迟外部时钟信号; 第二分频器，对从延迟电路提供的信号的频率进行分频，以产生第二内部时钟信号; 以及数据控制单元，根据第一内部时钟信号和第二内部时钟信号输出数据。

    Semiconductor memory and method of controlling data therefrom
    23.
    发明授权
    Semiconductor memory and method of controlling data therefrom 失效
    半导体存储器及其数据的控制方法

    公开(公告)号：US6166964A

    公开(公告)日：2000-12-26

    申请号：US288573

    申请日：1999-04-09

    申请人： Tadao Aikawa

    发明人： Tadao Aikawa

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C7/1006 ,  G11C11/4097

    摘要： A semiconductor memory, such as a multibit DRAM, has a multiple cell array banks, each having multiple cell arrays. Rows of sense amplifiers are located near each of the cell arrays and extend in a first direction. Multiple rows of transfer switches, also extending in the first direction, are located adjacent to each of the cell array banks. A first data bus, which extends in a second direction which is perpendicular to the first direction, connects the sense amplifiers with the transfer switches. Multiple data buffer rows extend in the first direction near the transfer switches. A second data bus, extending in the first direction, connects the transfer switches with the data buffers. A layout pitch is defined by a spacing between adjacent lines of the first data bus. The transfer switches are placed in accordance with the defined layout pitch and the data buffers are placed according to a layout pitch determined by multiplying the defined layout pitch by the number of cell array banks.

    摘要翻译： 诸如多位DRAM的半导体存储器具有多个单元阵列组，每个具有多个单元阵列。 读出放大器的行位于每个单元阵列附近并且在第一方向上延伸。 也在第一方向上延伸的多行传送开关位于每个单元阵列组附近。 第一数据总线在垂直于第一方向的第二方向上延伸，将感测放大器与转换开关连接。 多个数据缓冲行在传送开关附近的第一个方向上延伸。 第二个数据总线沿第一个方向延伸，将传输开关与数据缓冲器连接起来。 布局间距由第一数据总线的相邻线之间的间隔定义。 转移开关根据定义的布局间距放置，并且数据缓冲器根据通过将定义的布局间距乘以单元阵列组的数量而确定的布局间距而放置。

    Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations
    24.
    发明授权
    Semiconductor memory device having a single line data bus and latch circuits for improved pipeline operations 失效
    半导体存储器件具有单线数据总线和用于改进管线操作的锁存电路

    公开(公告)号：US5978884A

    公开(公告)日：1999-11-02

    申请号：US880890

    申请日：1997-06-23

    申请人： Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

    发明人： Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C19/00 ,  G11C19/28 ,  G06F13/00 ,  G11C7/00

    CPC分类号： G11C7/1048 ,  G11C19/00 ,  G11C19/28 ,  G11C7/1039

    摘要： A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

    摘要翻译： 半导体存储器件使用波浪管线系统，其可以通过减少用于对存储器核心部分和输出电路之间的数据总线充电的电流来降低功耗。 单行数据总线发送从存储器核心部分输出的读取数据。 数据总线驱动电路输出读取的数据以发送到单个数据总线。 多个数据锁存电路中的每一个具有连接到数据总线的数据输入端子。 数据输入控制电路响应于数据总线驱动电路的操作，将数据总线上串行发送的读取数据并行输入数据锁存电路。 数据输出控制电路通过依次选择数据锁存电路的输出来以锁存顺序输出锁存的读取数据。

    Decoder circuit for a semiconductor memory device
    25.
    发明授权
    Decoder circuit for a semiconductor memory device 失效
    一种用于半导体存储器件的解码器电路

    公开(公告)号：US5889725A

    公开(公告)日：1999-03-30

    申请号：US915332

    申请日：1997-08-20

    申请人： Tadao Aikawa ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Shusaku Yamaguchi ,  Koichi Nishimura

    发明人： Tadao Aikawa ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Shusaku Yamaguchi ,  Koichi Nishimura

    IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/00

    CPC分类号： G11C8/10

    摘要： A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals. The second predecoders and the second predecode lines are provided at least in double in such a manner that inputs of the main decoders to be connected to each of the second predecode lines are equal in number to inputs of the main decoders to be connected to each of the first predecode lines. It is possible to shorten the transition time of predecode signals because of the same capacitive load of the predecoder circuit.

    摘要翻译： 半导体或存储器件具有用于解码多个外部地址信号的解码器电路。 外部地址信号包括第一和第二外部地址信号。 第一地址缓冲器接收第一外部地址信号，并将第一内部地址信号输出到第一地址线。 第二地址缓冲器接收第二外部地址信号，并将第二内部地址信号输出到第二地址线。 第一预解码器具有连接到第一地址线的输入端，并将第一预解码信号输出到第一预解码线。 第二预解码器具有连接到第二地址线的输入端，并将第二预解码信号输出到第二预解码线。 主解码器具有连接到第一预解码线和第二预解码线并输出解码信号的输入端。 第一外部地址信号的数量大于第二外部地址信号的数量。 第二预解码器和第二预解码线以至少两个方式提供，使得要连接到每个第二预解码线的主解码器的输入数量等于要连接到每个的主解码器的输入 第一个预先代码行。 由于预解码器电路的容性负载相同，可以缩短预解码信号的转换时间。

    Semiconductor memory
    27.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US06735101B2

    公开(公告)日：2004-05-11

    申请号：US10390594

    申请日：2003-03-19

    申请人： Tadao Aikawa

    发明人： Tadao Aikawa

    IPC分类号： G11C1500

    CPC分类号： G11C15/00

    摘要： A semiconductor memory that reduces power consumed by a CAM. A storage circuit has stored a plurality of patterns of information indicative of whether to activate each memory word block. If specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit is input, an activation circuit activates each content addressable memory word block according to a specified pattern. If data to be retrieved is input, a specification circuit specifies a content addressable memory word which has stored data corresponding to the data to be retrieved from among a group of content addressable memory words activated by the activation circuit. As a result, activation will be performed by the content addressable memory word block. Therefore, by activating only necessary content addressable memory words, consumption of power can be reduced.

    摘要翻译： 一种降低CAM消耗功率的半导体存储器。 存储电路已经存储了指示是否激活每个存储器字块的多个信息模式。 如果输入了已经存储在存储电路中的多个信息模式中指定预定模式的指定信息，则激活电路根据指定的模式激活每个内容可寻址存储器字块。 如果输入要检索的数据，则指定电路指定内容可寻址存储器字，该内容可寻址存储器字已经存储与由激活电路激活的一组内容可寻址存储器字中的要检索的数据相对应的数据。 结果，将由内容可寻址存储器字块执行激活。 因此，通过仅激活必需的可寻址存储字，可以减少功率消耗。

    Semiconductor integrated circuit system
    29.
    发明授权
    Semiconductor integrated circuit system 失效
    半导体集成电路系统

    公开(公告)号：US5874853A

    公开(公告)日：1999-02-23

    申请号：US863356

    申请日：1997-05-27

    申请人： Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

    发明人： Shusaku Yamaguchi ,  Atsushi Hatakeyama ,  Masato Takita ,  Tadao Aikawa ,  Hirohiko Mochizuki

    IPC分类号： G11C11/413 ,  G11C11/407 ,  G11C11/409 ,  H03K17/22 ,  H03L7/00

    CPC分类号： H03K17/223 ,  Y10T307/724

    摘要： A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.

    摘要翻译： 半导体集成电路系统包括提供第一源电源电压的第一电源线和提供第二源电源电压的第二电源线。 当检测到第一源电源电压的上升沿时，第一边缘检测单元输出第一边沿检测信号。 当检测到第二源电源电压的上升沿时，第二边缘检测单元输出第二边缘检测信号。 输出单元连接到第一电力线，并且在数据输出周期中向数据终端输出数据，并且响应于第一边缘检测信号将数据端子设置为高阻抗状态。 输出控制单元连接到第二电力线，并且根据数据输出周期中的读取数据信号来控制输出单元，并且响应于第二边缘检测信号来控制输出单元，使得数据终端 通过输出单元设置在高阻抗状态。