公开(公告)号：US11121078B2

公开(公告)日：2021-09-14

申请号：US16573769

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L23/522 ,  G11C5/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/092 ,  G06F30/394

Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

公开(公告)号：US20200176303A1

公开(公告)日：2020-06-04

申请号：US16450278

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L27/11 ,  H01L21/3065

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US10651178B2

公开(公告)日：2020-05-12

申请号：US15896499

申请日：2018-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US09620509B1

公开(公告)日：2017-04-11

申请号：US14928685

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao Pao ,  Chang-Ta Yang ,  Feng-Ming Chang ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  G11C5/06 ,  G11C5/063 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L23/528 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7827

Abstract: An SRAM includes an SRAM array including a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

公开(公告)号：US11942169B2

公开(公告)日：2024-03-26

申请号：US17813891

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Kian-Long Lim ,  Wen-Chun Keng ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: G11C17/18 ,  G11C7/18 ,  H10B20/00

CPC classification number: G11C17/18 ,  G11C7/18 ,  H10B20/00

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20230369496A1

公开(公告)日：2023-11-16

申请号：US18359034

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/76224 ,  H01L21/02579 ,  H01L21/02576 ,  H01L21/02532

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

公开(公告)号：US11600623B2

公开(公告)日：2023-03-07

申请号：US16657421

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/11 ,  G11C11/412 ,  G06F30/30

Abstract: Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.

公开(公告)号：US20220359536A1

公开(公告)日：2022-11-10

申请号：US17873626

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/11 ,  G11C11/412 ,  G06F30/30

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US11462282B2

公开(公告)日：2022-10-04

申请号：US16837227

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Kian-Long Lim ,  Wen-Chun Keng ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: G11C17/18 ,  G11C7/18 ,  H01L27/112

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

公开(公告)号：US20220246465A1

公开(公告)日：2022-08-04

申请号：US17682425

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L21/3065 ,  H01L27/11

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.