公开(公告)号：US10770134B2

公开(公告)日：2020-09-08

申请号：US16202584

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen Lin ,  Wei-Min Chan ,  Chih-Yu Lin ,  Shih-Lien Linus Lu ,  Yen-Huei Chen

IPC: G06F21/00 ,  G11C11/419 ,  G11C11/418 ,  H04L9/32 ,  G11C7/20 ,  G11C7/24 ,  G11C11/413 ,  G09C1/00 ,  G11C29/44

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

公开(公告)号：US10734066B2

公开(公告)日：2020-08-04

申请号：US15800443

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C7/12 ,  H03K19/013 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/418 ,  G11C8/08

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US20190096478A1

公开(公告)日：2019-03-28

申请号：US16202584

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen LIN ,  Wei-Min Chan ,  Chih-Yu Lin ,  Shih-Lien Linus Lu ,  Yen-Huei Chen

IPC: G11C11/419 ,  H04L9/32 ,  G11C11/418 ,  G09C1/00 ,  G11C11/413 ,  G11C7/24 ,  G11C7/20 ,  G11C29/44

CPC classification number: G11C11/419 ,  G09C1/00 ,  G11C7/20 ,  G11C7/24 ,  G11C11/413 ,  G11C11/418 ,  G11C2029/4402 ,  H04L9/3278

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

公开(公告)号：US10153035B2

公开(公告)日：2018-12-11

申请号：US15288342

申请日：2016-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen Lin ,  Wei Min Chan ,  Chih-Yu Lin ,  Shih-Lien Linus Lu ,  Yen-Huei Chen

IPC: G06F21/00 ,  G11C11/419 ,  G11C11/418 ,  H04L9/32 ,  G11C7/20 ,  G11C7/24 ,  G11C11/413 ,  G11C29/44

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

公开(公告)号：US09997436B2

公开(公告)日：2018-06-12

申请号：US15379537

申请日：2016-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/10 ,  G11C5/06 ,  G11C7/18 ,  H01L27/06

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US20170098596A1

公开(公告)日：2017-04-06

申请号：US15379537

申请日：2016-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L27/10 ,  G11C5/06 ,  H01L25/065

CPC classification number: H01L23/481 ,  G11C5/063 ,  G11C7/18 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US12230318B2

公开(公告)日：2025-02-18

申请号：US17871635

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin Nien ,  Wei-Chang Zhao ,  Chih-Yu Lin ,  Hidehiro Fujiwara ,  Yen-Huei Chen ,  Ru-Yu Wang

IPC: G11C11/419 ,  G11C5/06 ,  G11C11/412

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

公开(公告)号：US11574674B2

公开(公告)日：2023-02-07

申请号：US17014622

申请日：2020-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen Lin ,  Wei Min Chan ,  Chih-Yu Lin ,  Shih-Lien Linus Lu ,  Yen-Huei Chen

IPC: G06F21/00 ,  G11C11/419 ,  G11C11/418 ,  H04L9/32 ,  G11C7/20 ,  G11C7/24 ,  G11C11/413 ,  G09C1/00 ,  G11C29/44

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

公开(公告)号：US11264088B2

公开(公告)日：2022-03-01

申请号：US16997857

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng Wu ,  Chih-Yu Lin ,  Kao-Cheng Lin ,  Wei-Min Chan ,  Yen-Huei Chen

IPC: G11C11/419 ,  G11C11/413 ,  H01L27/11 ,  G11C11/412

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

公开(公告)号：US20210201999A1

公开(公告)日：2021-07-01

申请号：US17186539

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/04 ,  H01L27/02

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.