公开(公告)号：US20220352354A1

公开(公告)日：2022-11-03

申请号：US17865113

申请日：2022-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hung Lin ,  Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

公开(公告)号：US20220351986A1

公开(公告)日：2022-11-03

申请号：US17866908

申请日：2022-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Yu LIN ,  Shih-Chi Kuo ,  Chun-Chieh Mo

IPC: H01L21/67 ,  H01L21/02 ,  H01L21/673 ,  H01L21/687

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

公开(公告)号：US11289647B2

公开(公告)日：2022-03-29

申请号：US15788690

申请日：2017-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

公开(公告)号：US11158790B2

公开(公告)日：2021-10-26

申请号：US16901450

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L27/22 ,  H01L27/24 ,  H01L45/00

Abstract: A memory cell includes: a first electrode contact formed as a cylinder shape that extends along a first direction; a resistive material layer comprising a first portion that extends along the first direction and surrounds the first electrode contact; and a second electrode contact coupled to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.

公开(公告)号：US11024671B2

公开(公告)日：2021-06-01

申请号：US16843635

申请日：2020-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo ,  Tsai-Hao Hung

IPC: H01L27/24 ,  C23C16/34 ,  H01L29/792 ,  H01L21/28 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.

公开(公告)号：US20210119024A1

公开(公告)日：2021-04-22

申请号：US17115831

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hung Lin ,  Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423

Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.

公开(公告)号：US10686129B2

公开(公告)日：2020-06-16

申请号：US16123519

申请日：2018-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L27/22 ,  H01L45/00 ,  H01L27/24

Abstract: A memory cell includes: a first electrode contact formed as a cylinder shape that extends along a first direction; a resistive material layer comprising a first portion that extends along the first direction and surrounds the first electrode contact; and a second electrode contact coupled to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.

公开(公告)号：US10680172B2

公开(公告)日：2020-06-09

申请号：US16163986

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

公开(公告)号：US20190164585A1

公开(公告)日：2019-05-30

申请号：US15965872

申请日：2018-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo

IPC: G11C11/16 ,  G11C8/14 ,  G11C7/18 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C7/18 ,  G11C8/14 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

公开(公告)号：US09972771B2

公开(公告)日：2018-05-15

申请号：US15080569

申请日：2016-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Mo ,  Shih-Chi Kuo ,  Tsung-Hsien Lee ,  Wu-An Weng ,  Chung-Yu Lin

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.