公开(公告)号：US20220020919A1

公开(公告)日：2022-01-20

申请号：US16933914

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Mauricio MANFRINI

IPC: H01L43/04 ,  H01L43/06 ,  H01L27/22 ,  H01L43/10 ,  H01L43/14

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

公开(公告)号：US20210399136A1

公开(公告)日：2021-12-23

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L21/447 ,  H01L21/383

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.

公开(公告)号：US20210225647A1

公开(公告)日：2021-07-22

申请号：US17224981

申请日：2021-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US10991576B2

公开(公告)日：2021-04-27

申请号：US16585571

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US20210098633A1

公开(公告)日：2021-04-01

申请号：US16588453

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US10332970B2

公开(公告)日：2019-06-25

申请号：US15194807

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis ,  Gerben Doornbos

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/10

Abstract: A method includes the following operations: (i) receiving a FET precursor including a first fin and a second fin, each of the first fin and the second fin having nanowire channels and sacrificial layers; (ii) forming a dummy gate traversing the first and second fins, thereby defining channel regions of the first and second fins under the dummy gate; (iii) forming source/drain features from exposed portions of the first and second fins; (iv) removing the dummy gate to expose the channel regions of the first and second fins; and (v) suspending the nanowire channels of the first and second fins by removing portions of the sacrificial layers of the first and second fins.

公开(公告)号：US20140264443A1

公开(公告)日：2014-09-18

申请号：US13794914

申请日：2013-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Georgios Vellianitis

IPC: H01L29/201 ,  H01L29/20

CPC classification number: H01L21/28255 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density.

Abstract translation: 本公开涉及具有锗盖层的晶体管器件，其能够提供低界面陷阱密度，同时满足有效的氧化物厚度缩放要求，以及相关的制造方法。 在一些实施例中，所公开的晶体管器件具有在源极区域和漏极区域之间的位置处设置在半导体主体内的沟道层。 锗覆盖层设置在沟道层上。 栅极电介质层通过锗覆盖层与沟道层分离，并且栅极区域设置在栅极介电层的上方。 将栅极介电层与沟道层分离允许锗覆盖层防止原子从沟道层扩散到栅极介电层中，从而提供低的界面陷阱密度。

公开(公告)号：US12148828B2

公开(公告)日：2024-11-19

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L21/383 ,  H01L21/447 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.

公开(公告)号：US12080771B2

公开(公告)日：2024-09-03

申请号：US18175221

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Blandine Duriez

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L21/02675 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10−9 Ω-cm2.

公开(公告)号：US12051702B2

公开(公告)日：2024-07-30

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/78696 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/78618

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.