公开(公告)号：US20220077062A1

公开(公告)日：2022-03-10

申请号：US17161789

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L23/535 ,  H01L23/48 ,  H01L27/12 ,  H01L27/088 ,  H01L21/74 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a gate structure overlying a front-side surface of a first substrate. The first substrate has a back-side surface opposite the front-side surface. A first source/drain structure overlies the first substrate and is laterally adjacent to the grate structure. A power rail is embedded in the first substrate and directly underlies the first source/drain structure. A first source/drain contact continuously extends from the first source/drain structure to the power rail. The first source/drain contact electrically couples the first source/drain structure to the power rail.

公开(公告)号：US20210391469A1

公开(公告)日：2021-12-16

申请号：US16901004

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Blandine Duriez ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

公开(公告)号：US11088337B2

公开(公告)日：2021-08-10

申请号：US16590115

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

公开(公告)号：US20210098632A1

公开(公告)日：2021-04-01

申请号：US16586790

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L21/311 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

公开(公告)号：US20200311524A1

公开(公告)日：2020-10-01

申请号：US16371382

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Mauricio Manfrini

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.

公开(公告)号：US10770358B2

公开(公告)日：2020-09-08

申请号：US16201694

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US10332965B2

公开(公告)日：2019-06-25

申请号：US15588804

申请日：2017-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher Holland ,  Mark Van Dal ,  Georgios Vellianitis ,  Blandine Duriez ,  Gerben Doornbos

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.

公开(公告)号：US20240021699A1

公开(公告)日：2024-01-18

申请号：US18359106

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L29/517 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/6684

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

公开(公告)号：US11742292B2

公开(公告)日：2023-08-29

申请号：US17161789

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L23/485 ,  H01L23/528 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L27/092 ,  H01L23/535 ,  H01L21/74 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12 ,  H01L23/482

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L23/481 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4175 ,  H01L29/66742 ,  H01L23/485 ,  H01L23/4825

Abstract: The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a gate structure overlying a front-side surface of a first substrate. The first substrate has a back-side surface opposite the front-side surface. A first source/drain structure overlies the first substrate and is laterally adjacent to the grate structure. A power rail is embedded in the first substrate and directly underlies the first source/drain structure. A first source/drain contact continuously extends from the first source/drain structure to the power rail. The first source/drain contact electrically couples the first source/drain structure to the power rail.

公开(公告)号：US11710775B2

公开(公告)日：2023-07-25

申请号：US16888349

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.