公开(公告)号：US11201243B2

公开(公告)日：2021-12-14

申请号：US16559343

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Han-Yu Lin ,  Chun-Yu Chen ,  Chih-Ching Wang ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Li-Te Lin ,  Gwan-Sin Chang ,  Pinyen Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

公开(公告)号：US20210327764A1

公开(公告)日：2021-10-21

申请号：US17362025

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

公开(公告)号：US20240347345A1

公开(公告)日：2024-10-17

申请号：US18751423

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Li-Te Lin ,  Pinyen Lin ,  Tze-Chung Lin

IPC: H01L21/311 ,  C23C16/452 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/311 ,  C23C16/452 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67225 ,  H01L21/67248 ,  H01L21/67748

Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.

公开(公告)号：US20240274485A1

公开(公告)日：2024-08-15

申请号：US18324036

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Chi Shih ,  Ku-Feng Yang ,  Han-Yu Lin ,  Wei-Yen Woon ,  Szuya Liao

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5286 ,  H01L27/12 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/29186 ,  H01L2224/32225 ,  H01L2224/83193 ,  H01L2224/83896 ,  H01L2924/0504 ,  H01L2924/05442 ,  H01L2924/059

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a power rail. The device further includes a carrier substrate bonded to the first interconnect structure and a first heat dissipation layer contacting the carrier substrate.

公开(公告)号：US12062576B2

公开(公告)日：2024-08-13

申请号：US17533372

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Szu-Hua Chen ,  Kuan-Kan Hu ,  Kenichi Sano ,  Po-Cheng Wang ,  Wei-Yen Woon ,  Pinyen Lin ,  Che Chi Shih

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78618 ,  H01L29/78672 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

公开(公告)号：US20230282520A1

公开(公告)日：2023-09-07

申请号：US18313783

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L27/0886 ,  H01L21/26586 ,  H01L21/823481 ,  H01L21/764 ,  H01L21/31053 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/0228

Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

公开(公告)号：US11646234B2

公开(公告)日：2023-05-09

申请号：US17362025

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/26586 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/764 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

公开(公告)号：US11056393B2

公开(公告)日：2021-07-06

申请号：US16298720

申请日：2019-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Yi-Ruei Jhan ,  Fang-Wei Lee ,  Tze-Chung Lin ,  Chao-Hsien Huang ,  Li-Te Lin ,  Pinyen Lin ,  Akira Mineji

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

公开(公告)号：US20210066490A1

公开(公告)日：2021-03-04

申请号：US16559343

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Han-Yu Lin ,  Chun-Yu Chen ,  Chih-Ching Wang ,  Fang-Wei Lee ,  Tze-Chung LIN ,  Li-Te LIN ,  Gwan-Sin Chang ,  Pinyen LIN

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

公开(公告)号：US20200006062A1

公开(公告)日：2020-01-02

申请号：US16259345

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Han-Yu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/40

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.