公开(公告)号：US20220059524A1

公开(公告)日：2022-02-24

申请号：US16996986

申请日：2020-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chia HSU ,  Tung-Heng HSIEH ,  Yung-Feng CHANG ,  Bao-Ru YOUNG ,  Jam-Wem LEE ,  Chih-Hung WANG

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

公开(公告)号：US20200258878A1

公开(公告)日：2020-08-13

申请号：US16861809

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Feng CHANG ,  Jam-Wem LEE ,  Li-Wei CHU ,  Po-Lin PENG

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/861 ,  H01L27/08 ,  H01L27/06

Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.

公开(公告)号：US20170040311A1

公开(公告)日：2017-02-09

申请号：US15332999

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Che TSAI ,  Jam-Wem LEE

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H02H9/04

CPC classification number: H01L27/0281 ,  H01L21/822 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/8613 ,  H01L29/87 ,  H02H9/046

Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

Abstract translation: 具有用于CMOS IC器件的ESD保护的多个二极管的二极管串包括二极管串中的第一二极管和最后一个二极管，其中第一二极管和最后一个二极管都形成在硅衬底的底层上，以及 二极管串中的剩余二极管。 剩余的二极管形成在位于底层顶部的顶层上。 二极管串还包括多个导线，其将底层上的第一二极管和最后一个二极管依次连接到顶层上的剩余二极管，以形成二极管串的三维（3D）结构。

公开(公告)号：US20140376133A1

公开(公告)日：2014-12-25

申请号：US13921226

申请日：2013-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yen LIN ,  Jam-Wem LEE

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H02H9/046

Abstract: A device includes a first bidirectional PNP circuit coupled to a first output of an communication circuit, and a second bidirectional PNP circuit coupling to a second output of the communication circuit. The first and second bi-direction PNP circuits have coupled outputs and a first breakdown voltage. A third bidirectional PNP circuit is coupled to ground via the coupled outputs of the first bidirectional PNP circuit and of the second bidirectional PNP circuit. The third bidirectional PNP circuit has a second breakdown voltage. In some arrangements, a sum of the first breakdown voltage and the second breakdown voltage exceeds 60 volts. The communication circuit can be an automotive application circuit for a serial automotive communication application. The first and second bidirectional transistor circuits can form a part of a cell of an integrated circuit having an isolation structure to sustain high voltage.

Abstract translation: 一种设备包括耦合到通信电路的第一输出的第一双向PNP电路和耦合到通信电路的第二输出的第二双向PNP电路。 第一和第二双向PNP电路具有耦合输出和第一击穿电压。 第三双向PNP电路经由第一双向PNP电路和第二双向PNP电路的耦合输出耦合到地。 第三双向PNP电路具有第二击穿电压。 在一些布置中，第一击穿电压和第二击穿电压之和超过60伏特。 通信电路可以是用于串行汽车通信应用的汽车应用电路。 第一和第二双向晶体管电路可以形成具有隔离结构以保持高电压的集成电路的单元的一部分。

公开(公告)号：US20240387511A1

公开(公告)日：2024-11-21

申请号：US18789462

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Jam-Wem LEE

IPC: H01L27/02

Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.

公开(公告)号：US20240363621A1

公开(公告)日：2024-10-31

申请号：US18770552

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung YEH ,  Wun-Jie LIN ,  Jam-Wem LEE

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

公开(公告)号：US20240079408A1

公开(公告)日：2024-03-07

申请号：US18508015

申请日：2023-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Po-Lin PENG ,  Jam-Wem LEE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/87

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/87

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

公开(公告)号：US20220208751A1

公开(公告)日：2022-06-30

申请号：US17698730

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Jam-Wem LEE

IPC: H01L27/02

Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.

公开(公告)号：US20220130825A1

公开(公告)日：2022-04-28

申请号：US17570909

申请日：2022-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Po-Lin PENG ,  Jam-Wem LEE

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/87

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

公开(公告)号：US20220029414A1

公开(公告)日：2022-01-27

申请号：US16936236

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Yu-Ti SU ,  Chia-Wei HSU ,  Ming-Fu TSAI ,  Shu-Yu SU ,  Li-Wei CHU ,  Jam-Wem LEE ,  Chia-Jung CHANG ,  Hsiang-Hui CHENG

IPC: H02H9/04 ,  H02H1/00 ,  G01R31/00

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.