公开(公告)号：US20220367355A1

公开(公告)日：2022-11-17

申请号：US17815381

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co, Ltd.

发明人： Chao-Chun Wang ,  Chung-Chi Ko ,  Po-Cheng Shih

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

摘要： An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

公开(公告)号：US11282742B2

公开(公告)日：2022-03-22

申请号：US16655961

申请日：2019-10-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Cheng Shih ,  Tze-Liang Lee ,  Jen-Hung Wang ,  Yu-Kai Lin ,  Su-Jen Sung

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/02

摘要： A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.

公开(公告)号：US20210265204A1

公开(公告)日：2021-08-26

申请号：US17094700

申请日：2020-11-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC分类号： H01L21/768 ,  H01L21/027 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20

摘要： A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US10910216B2

公开(公告)日：2021-02-02

申请号：US15944627

申请日：2018-04-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia Cheng Chou ,  Li Chun Te ,  Po-Cheng Shih ,  Tien-I Bao

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  C23C16/30 ,  H01L23/532 ,  H01L23/535

摘要： Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

公开(公告)号：US20240120236A1

公开(公告)日：2024-04-11

申请号：US18306716

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-Jung Kuo ,  Po-Cheng Shih ,  Wan Chen Hsieh ,  Zhen-Cheng Wu ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/823481 ,  H01L27/0886

摘要： A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

公开(公告)号：US20230317469A1

公开(公告)日：2023-10-05

申请号：US17711885

申请日：2022-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bor Chiuan Hsieh ,  Po-Hsien Cheng ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/456 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897

摘要： A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

公开(公告)号：US20220246473A1

公开(公告)日：2022-08-04

申请号：US17524830

申请日：2021-11-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jian-Hong Lu ,  Tsai-Jung Ho ,  Bor Chiuan Hsieh ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

摘要： A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a metal gate over the fin, the metal gate being surround by a dielectric layer; etching the metal gate to reduce a height of the metal gate, where after the etching, a recess is formed over the metal gate between gate spacers of the metal gate; lining sidewalls and a bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a mask layer over the metal gate, where a first opening of the mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source/drain region; and filling the second opening with a conductive material.

公开(公告)号：US11374127B2

公开(公告)日：2022-06-28

申请号：US16939199

申请日：2020-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8238 ,  H01L27/092

摘要： A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US11328952B2

公开(公告)日：2022-05-10

申请号：US17099263

申请日：2020-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Chou ,  Chih-Chien Chi ,  Chung-Chi Ko ,  Yao-Jen Chang ,  Chen-Yuan Kao ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Tze-Liang Lee ,  Jun-Yi Ruan

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/84 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08

摘要： A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20210057340A1

公开(公告)日：2021-02-25

申请号：US17077556

申请日：2020-10-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Chun Wang ,  Chung-Chi Ko ,  Po-Cheng Shih

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

摘要： An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.