公开(公告)号：US20230223364A1

公开(公告)日：2023-07-13

申请号：US18186348

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/538 ,  H01Q21/06 ,  H01Q9/28 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L23/49822 ,  H01L23/5383 ,  H01Q21/062 ,  H01Q21/065 ,  H01Q9/285 ,  H01Q9/045 ,  H01L2224/16227 ,  H01L24/16

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US20220359485A1

公开(公告)日：2022-11-10

申请号：US17813873

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yi Yang ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L25/18 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538

Abstract: A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

公开(公告)号：US11380666B2

公开(公告)日：2022-07-05

申请号：US17068026

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US20220189919A1

公开(公告)日：2022-06-16

申请号：US17688448

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

公开(公告)号：US11270953B2

公开(公告)日：2022-03-08

申请号：US16284630

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng ,  Shuo-Mao Chen ,  Ming-Chih Yew

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H05K1/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

公开(公告)号：US11239173B2

公开(公告)日：2022-02-01

申请号：US16446796

申请日：2019-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Techi Wong ,  Shin-Puu Jeng

IPC: H01L21/98 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

公开(公告)号：US20210351118A1

公开(公告)日：2021-11-11

申请号：US17383953

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US11094625B2

公开(公告)日：2021-08-17

申请号：US16406600

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Techi Wong ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Shih-Ting Hung ,  Shin-Puu Jeng

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

公开(公告)号：US10515827B2

公开(公告)日：2019-12-24

申请号：US15874541

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/498 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip. The method includes bonding an interposer substrate to the redistribution structure through a conductive structure. The chip is between the interposer substrate and the redistribution structure. The interposer substrate has a recess adjacent to the redistribution structure. A first portion of the chip is in the recess. The interposer substrate includes a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure.

公开(公告)号：US10347574B2

公开(公告)日：2019-07-09

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L23/498 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/373 ,  H01L25/075 ,  H01L23/36 ,  H01L23/367

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.