公开(公告)号：US12051622B2

公开(公告)日：2024-07-30

申请号：US17112119

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/60

CPC classification number: H01L21/76877 ,  H01L21/4825 ,  H01L21/76802 ,  H01L23/53228 ,  H01L24/14 ,  H01L2021/60022

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US20200013707A1

公开(公告)日：2020-01-09

申请号：US16504324

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US20240379428A1

公开(公告)日：2024-11-14

申请号：US18780044

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/60 ,  H01L23/00 ,  H01L23/532

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US10347574B2

公开(公告)日：2019-07-09

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/04 ,  H01L25/07 ,  H01L25/11 ,  H01L23/498 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/373 ,  H01L25/075 ,  H01L23/36 ,  H01L23/367

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US20220384259A1

公开(公告)日：2022-12-01

申请号：US17818640

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/00

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US20190096791A1

公开(公告)日：2019-03-28

申请号：US15876227

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/49822 ,  H01L21/56 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/81 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US09607999B2

公开(公告)日：2017-03-28

申请号：US14880997

申请日：2015-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Tai Lu ,  Chih-Hsien Lin

IPC: H01L27/115 ,  H01L21/3205 ,  G11C29/04 ,  H01L21/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/22 ,  H01L21/66

CPC classification number: H01L27/11521 ,  G11C16/02 ,  G11C16/0416 ,  G11C16/225 ,  G11C29/04 ,  G11C2029/0403 ,  H01L21/28273 ,  H01L21/3205 ,  H01L22/14 ,  H01L27/11558

Abstract: A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (UV) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.