公开(公告)号：US20240021706A1

公开(公告)日：2024-01-18

申请号：US18366460

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/0665 ,  H01L21/0228 ,  H01L29/42392

Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US11605635B2

公开(公告)日：2023-03-14

申请号：US17186293

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/113 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20230038762A1

公开(公告)日：2023-02-09

申请号：US17650112

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Szu-Ying Chen ,  Po-Kang Ho ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762

Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

公开(公告)号：US20220359311A1

公开(公告)日：2022-11-10

申请号：US17385561

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US20200321373A1

公开(公告)日：2020-10-08

申请号：US16909024

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

公开(公告)号：US10734428B2

公开(公告)日：2020-08-04

申请号：US16212784

申请日：2018-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector.

公开(公告)号：US20190115376A1

公开(公告)日：2019-04-18

申请号：US16212784

申请日：2018-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14689

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector

公开(公告)号：US09853082B2

公开(公告)日：2017-12-26

申请号：US15144998

申请日：2016-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Dun-Nian Yaung ,  Chen-Jong Wang ,  Tzu-Hsuan Hsu

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14689

Abstract: A color filter array and micro-lens structure for imaging system and method of forming the color filter array and micro-lens structure. A micro-lens material is used to fill the space between the color filters to re-direct incident radiation, and form a convex micro-lens structure above a top surface of the color filters.

公开(公告)号：US20240379461A1

公开(公告)日：2024-11-14

申请号：US18784355

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US12087847B2

公开(公告)日：2024-09-10

申请号：US17809976

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chien-Tai Chan ,  Liang-Yin Chen ,  Yee-Chia Yeo ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.