公开(公告)号：US12266687B2

公开(公告)日：2025-04-01

申请号：US17650712

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Yee-Chia Yeo

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

公开(公告)号：US12266574B2

公开(公告)日：2025-04-01

申请号：US17738527

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Li-Chi Yu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/3105 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

公开(公告)号：US12199156B2

公开(公告)日：2025-01-14

申请号：US17650329

申请日：2022-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Yi-Syuan Siao ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

公开(公告)号：US12191212B2

公开(公告)日：2025-01-07

申请号：US17737766

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Li ,  Pin-Ju Liang ,  Ta-Chun Ma ,  Pei-Ren Jeng ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L27/092

Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

公开(公告)号：US20240405070A1

公开(公告)日：2024-12-05

申请号：US18780842

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

公开(公告)号：US20240379461A1

公开(公告)日：2024-11-14

申请号：US18784355

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US20240379446A1

公开(公告)日：2024-11-14

申请号：US18782255

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/223 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

公开(公告)号：US20240371930A1

公开(公告)日：2024-11-07

申请号：US18769934

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Wei-Jen Lai ,  Chien-I Kuo ,  Wei-Yuan Lu ,  Chia-Pin Lin ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a nanostructure; and a source/drain region adjoining a channel region of the nanostructure, the source/drain region including: a first epitaxial layer on a sidewall of the nanostructure, the first epitaxial layer including a germanium-free semiconductor material and a p-type dopant; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a germanium-containing semiconductor material and the p-type dopant; and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including the germanium-containing semiconductor material and the p-type dopant.

公开(公告)号：US20240355826A1

公开(公告)日：2024-10-24

申请号：US18760800

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chi Tai ,  Yi-Fang Pai ,  Tsz-Mei Kwok ,  Tsung-Hsi Yang ,  Jeng-Wei Yu ,  Cheng-Hsiung Yen ,  Jui-Hsuan Chen ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Heng-Wen Ting ,  Ming-Hua Yu

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

公开(公告)号：US12094778B2

公开(公告)日：2024-09-17

申请号：US17490922

申请日：2021-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Wei Yu ,  Yi-Fang Pai ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.