公开(公告)号：US20210083042A1

公开(公告)日：2021-03-18

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US20190148389A1

公开(公告)日：2019-05-16

申请号：US16022702

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/40 ,  H01L21/765 ,  H01L23/00

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US20190148375A1

公开(公告)日：2019-05-16

申请号：US15989648

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238

Abstract: In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.

公开(公告)号：US11631682B2

公开(公告)日：2023-04-18

申请号：US16860234

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  G06F30/398 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US20230069119A1

公开(公告)日：2023-03-02

申请号：US17461476

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Te-Hsin Chiu ,  Jiann-Tyng Tzeng

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L25/11 ,  H01L23/522

Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

公开(公告)号：US11532694B2

公开(公告)日：2022-12-20

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L23/64 ,  H01L29/92 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/768

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US10971590B2

公开(公告)日：2021-04-06

申请号：US16661108

申请日：2019-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.

公开(公告)号：US20210043638A1

公开(公告)日：2021-02-11

申请号：US16535431

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu

IPC: H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L21/265

Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

公开(公告)号：US10861951B2

公开(公告)日：2020-12-08

申请号：US16550497

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming an isolation structure within an upper surface of a substrate. The isolation structure surrounds a continuous region of the substrate defining a source area, a drain area, and a channel area. A gate structure is formed over the channel area. An implantation process is performed to form a source region within the source area and a drain region within the drain area. The channel area is arranged between the source region and the drain region along a first direction and extends past the source region and the drain region along a second direction that is perpendicular to the first direction. The first direction and the second direction are parallel to the upper surface of the substrate.

公开(公告)号：US20200321337A1

公开(公告)日：2020-10-08

申请号：US16906031

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.