公开(公告)号：US20240379557A1

公开(公告)日：2024-11-14

申请号：US18782167

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US11929328B2

公开(公告)日：2024-03-12

申请号：US17140654

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L21/32135 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76865 ,  H01L29/41725 ,  H01L21/31111 ,  H01L21/31116

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US20240079332A1

公开(公告)日：2024-03-07

申请号：US18504714

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L21/32135 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76865 ,  H01L29/41725 ,  H01L21/31116

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US11603602B2

公开(公告)日：2023-03-14

申请号：US17238080

申请日：2021-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko Jangjian ,  Yu-Ren Peng ,  Yao-Hsiang Liang ,  Ting-Chun Wang

IPC: C25D7/12 ,  C25D21/12 ,  C25D3/38 ,  H01L21/768 ,  C25D17/00

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

公开(公告)号：US11011641B2

公开(公告)日：2021-05-18

申请号：US16735495

申请日：2020-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Shiu-Ko Jangjian ,  Ting-Chun Wang

IPC: H01L27/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

公开(公告)号：US10062787B2

公开(公告)日：2018-08-28

申请号：US15415790

申请日：2017-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3215

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

公开(公告)号：US09985133B2

公开(公告)日：2018-05-29

申请号：US15332875

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Chih-Nan Wu ,  Chun-Che Lin ,  Ting-Chun Wang

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

公开(公告)号：US11230784B2

公开(公告)日：2022-01-25

申请号：US16677563

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko Jangjian ,  Ting-Chun Wang ,  Ing-Ju Lee

IPC: C25D21/12 ,  C25D3/38 ,  H01L21/768 ,  C25D7/12 ,  C25D17/00

Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

公开(公告)号：US10763338B2

公开(公告)日：2020-09-01

申请号：US15690693

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko Jang-Jian ,  Ting-Chun Wang ,  Chuan-Pu Liu

IPC: H01L29/45 ,  H01L29/66 ,  H01L21/768 ,  H01L21/326 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02

Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.

公开(公告)号：US20200043858A1

公开(公告)日：2020-02-06

申请号：US16050191

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.