公开(公告)号：US20210343332A1

公开(公告)日：2021-11-04

申请号：US17186322

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Chia-En Huang

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/11

Abstract: A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.

公开(公告)号：US20200006160A1

公开(公告)日：2020-01-02

申请号：US16393543

申请日：2019-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L23/522

Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.

公开(公告)号：US10096706B2

公开(公告)日：2018-10-09

申请号：US15615195

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Jhon Jhy Liaw ,  Wai-Yi Lien ,  Jia-Chuan You ,  Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Wei-Hao Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1158 ,  H01L27/11 ,  H01L21/822

Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.

公开(公告)号：US12243781B2

公开(公告)日：2025-03-04

申请号：US17874267

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US20240387530A1

公开(公告)日：2024-11-21

申请号：US18786788

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/50 ,  H01L27/02

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US12113066B2

公开(公告)日：2024-10-08

申请号：US18511533

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/50 ,  H01L27/0207

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US11851325B2

公开(公告)日：2023-12-26

申请号：US16695673

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Chang ,  Ya-Jen Sheuh ,  Ren-Dou Lee ,  Yi-Chih Chang ,  Yi-Hsun Chiu ,  Yuan-Hsin Chi

IPC: B81C1/00 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/66

CPC classification number: B81C1/00238 ,  H01L21/02274 ,  H01L21/31053 ,  H01L22/12

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US11664278B2

公开(公告)日：2023-05-30

申请号：US16935830

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823431 ,  H01L21/76816 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US20220336472A1

公开(公告)日：2022-10-20

申请号：US17810673

申请日：2022-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L29/423

Abstract: An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

公开(公告)号：US20210376076A1

公开(公告)日：2021-12-02

申请号：US17127095

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/092 ,  H01L23/538 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.