公开(公告)号：US20210151495A1

公开(公告)日：2021-05-20

申请号：US16684871

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC分类号： H01L27/146

摘要： The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US10854647B2

公开(公告)日：2020-12-01

申请号：US16364508

申请日：2019-03-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yimin Huang

IPC分类号： H01L27/146

摘要： In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate.

公开(公告)号：US10797091B2

公开(公告)日：2020-10-06

申请号：US16113101

申请日：2018-08-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Feng-Jia Shiu ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Chun-Wei Chang ,  Wei-Cheng Hsu ,  Wei Chuang Wu ,  Yimin Huang

IPC分类号： H01L27/146

摘要： In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

公开(公告)号：US09818788B2

公开(公告)日：2017-11-14

申请号：US15345868

申请日：2016-11-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhy-Jyi Sze ,  Alexander Kalnitsky ,  Yimin Huang

IPC分类号： H01L21/00 ,  H01L27/146

CPC分类号： H01L27/1464 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14656 ,  H01L27/14685 ,  H01L27/14689

摘要： A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.

公开(公告)号：US09515116B1

公开(公告)日：2016-12-06

申请号：US14835983

申请日：2015-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhy-Jyi Sze ,  Alexander Kalnitsky ,  Yimin Huang

IPC分类号： H01L31/0232 ,  H01L27/146

CPC分类号： H01L27/1464 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14656 ,  H01L27/14685 ,  H01L27/14689

摘要： A back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor using a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A semiconductor column extends vertically from a photodetector, towards a back-end-of-line (BEOL) stack. A floating diffusion region (FDR) is vertically spaced from the photodetector by the semiconductor column. The FDR comprises a sidewall surface laterally offset from a neighboring sidewall surface of the semiconductor column to define a lateral recess between the FDR and the photodetector. A gate dielectric layer lines the sidewall surface of the semiconductor column and is arranged in the lateral recess. A gate is arranged laterally adjacent to the gate dielectric layer and filling the lateral recess. Further, a method for manufacturing the vertical transfer gate structure is provided.

摘要翻译： 提供了使用垂直传输门结构提高量子效率（QE）和全局快门效率（GSE）的背面照明（BSI）互补金属氧化物半导体（CMOS）图像传感器。 半导体柱从光电检测器垂直延伸到后端（BEOL）堆叠。 浮动扩散区域（FDR）通过半导体柱与光电检测器垂直间隔开。 FDR包括从半导体柱的相邻侧壁表面横向偏移的侧壁表面，以在FDR和光电检测器之间限定横向凹槽。 栅极电介质层配置在半导体柱的侧壁表面并且布置在横向凹槽中。 栅极被布置成横向邻近栅极电介质层并填充侧向凹槽。 此外，提供了一种用于制造垂直传输门结构的方法。

公开(公告)号：US09496264B2

公开(公告)日：2016-11-15

申请号：US14621814

申请日：2015-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

发明人： Kai-Hsuan Lee ,  Cheng-Yu Yang ,  Hsiang-Ku Shen ,  Han-Ting Tsai ,  Yimin Huang

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L21/335 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L29/161 ,  H01L29/49

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/161 ,  H01L29/267 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.

摘要翻译： 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。

公开(公告)号：US11670663B2

公开(公告)日：2023-06-06

申请号：US17236343

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tung-Ting Wu ,  Jhy-Jyi Sze ,  Yimin Huang

IPC分类号： H01L27/146 ,  H01L31/036

CPC分类号： H01L27/14636 ,  H01L27/14607 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/036

摘要： The present disclosure, in some embodiments, relates to an image sensing integrated chip. The image sensing integrated chip includes a semiconductor substrate having sidewalls defining one or more trenches on opposing sides of a region of the semiconductor substrate. One or more dielectrics are disposed within the one or more trenches. The semiconductor substrate has a plurality of flat surfaces arranged between the one or more trenches. Adjacent ones of the plurality of flat surfaces define a plurality of triangular shaped protrusions and alternative ones of the plurality of flat surfaces are substantially parallel to one another, as viewed along a cross-sectional view.

公开(公告)号：US11348881B2

公开(公告)日：2022-05-31

申请号：US16589460

申请日：2019-10-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tung-Ting Wu ,  Chen-Jong Wang ,  Jen-Cheng Liu ,  Yimin Huang ,  Chin-Chia Kuo

IPC分类号： H01L23/58 ,  H01L27/146

摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

公开(公告)号：US11309348B2

公开(公告)日：2022-04-19

申请号：US16567210

申请日：2019-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Jhy-Jyi Sze ,  Yimin Huang

IPC分类号： H01L27/146 ,  H04N5/374

摘要： The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.

公开(公告)号：US20210074758A1

公开(公告)日：2021-03-11

申请号：US16567210

申请日：2019-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Jhy-Jyi Sze ,  Yimin Huang

IPC分类号： H01L27/146 ,  H04N5/374

摘要： The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.